Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8411290 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
57 |
| auto[1] |
6176882 |
1 |
|
|
T24 |
36 |
|
T25 |
1288 |
|
T27 |
110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982493 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
88 |
| auto[1] |
2605679 |
1 |
|
|
T24 |
5 |
|
T25 |
678 |
|
T27 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439593 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
86 |
| auto[1] |
6148579 |
1 |
|
|
T24 |
7 |
|
T25 |
1361 |
|
T27 |
77 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1767243 |
1 |
|
|
T25 |
358 |
|
T27 |
36 |
|
T28 |
94062 |
| auto[1] |
auto[0] |
auto[1] |
1301546 |
1 |
|
|
T24 |
3 |
|
T25 |
340 |
|
T27 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1775657 |
1 |
|
|
T24 |
2 |
|
T25 |
325 |
|
T27 |
28 |
| auto[1] |
auto[1] |
auto[1] |
1304133 |
1 |
|
|
T24 |
2 |
|
T25 |
338 |
|
T27 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |