Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426509 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
50 |
| auto[1] |
6161663 |
1 |
|
|
T24 |
43 |
|
T25 |
1308 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11975965 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
2612207 |
1 |
|
|
T25 |
668 |
|
T27 |
74 |
|
T28 |
113701 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8417901 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
83 |
| auto[1] |
6170271 |
1 |
|
|
T24 |
10 |
|
T25 |
1302 |
|
T27 |
135 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1786333 |
1 |
|
|
T25 |
322 |
|
T27 |
48 |
|
T28 |
92512 |
| auto[1] |
auto[0] |
auto[1] |
1310841 |
1 |
|
|
T25 |
341 |
|
T27 |
41 |
|
T28 |
56152 |
| auto[1] |
auto[1] |
auto[0] |
1771731 |
1 |
|
|
T24 |
10 |
|
T25 |
312 |
|
T27 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1301366 |
1 |
|
|
T25 |
327 |
|
T27 |
33 |
|
T28 |
57549 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |