Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431622 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
77 |
| auto[1] |
6156550 |
1 |
|
|
T24 |
16 |
|
T25 |
1360 |
|
T27 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11980998 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
2607174 |
1 |
|
|
T25 |
509 |
|
T27 |
40 |
|
T28 |
113043 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8432474 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
76 |
| auto[1] |
6155698 |
1 |
|
|
T24 |
17 |
|
T25 |
1068 |
|
T27 |
90 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780433 |
1 |
|
|
T24 |
11 |
|
T25 |
354 |
|
T27 |
24 |
| auto[1] |
auto[0] |
auto[1] |
1310628 |
1 |
|
|
T25 |
296 |
|
T27 |
18 |
|
T28 |
56738 |
| auto[1] |
auto[1] |
auto[0] |
1768091 |
1 |
|
|
T24 |
6 |
|
T25 |
205 |
|
T27 |
26 |
| auto[1] |
auto[1] |
auto[1] |
1296546 |
1 |
|
|
T25 |
213 |
|
T27 |
22 |
|
T28 |
56305 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |