Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8404611 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6183561 |
1 |
|
|
T24 |
24 |
|
T25 |
1266 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982218 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
2605954 |
1 |
|
|
T24 |
23 |
|
T25 |
718 |
|
T27 |
63 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8421022 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
49 |
| auto[1] |
6167150 |
1 |
|
|
T24 |
44 |
|
T25 |
1353 |
|
T27 |
122 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780903 |
1 |
|
|
T24 |
15 |
|
T25 |
318 |
|
T27 |
35 |
| auto[1] |
auto[0] |
auto[1] |
1299820 |
1 |
|
|
T24 |
13 |
|
T25 |
348 |
|
T27 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1780293 |
1 |
|
|
T24 |
6 |
|
T25 |
317 |
|
T27 |
24 |
| auto[1] |
auto[1] |
auto[1] |
1306134 |
1 |
|
|
T24 |
10 |
|
T25 |
370 |
|
T27 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |