Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8439895 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
61 |
| auto[1] |
6148277 |
1 |
|
|
T24 |
32 |
|
T25 |
1274 |
|
T27 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2677100 |
1 |
|
|
T24 |
26 |
|
T25 |
581 |
|
T27 |
38 |
| auto[1] |
auto[0] |
auto[1] |
393828 |
1 |
|
|
T25 |
142 |
|
T27 |
3 |
|
T28 |
19967 |
| auto[1] |
auto[1] |
auto[0] |
2685220 |
1 |
|
|
T24 |
6 |
|
T25 |
442 |
|
T27 |
44 |
| auto[1] |
auto[1] |
auto[1] |
392129 |
1 |
|
|
T25 |
109 |
|
T27 |
3 |
|
T28 |
19785 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |