Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8407839 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
45 |
| auto[1] |
6180333 |
1 |
|
|
T24 |
48 |
|
T25 |
1348 |
|
T27 |
106 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11975417 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
87 |
| auto[1] |
2612755 |
1 |
|
|
T24 |
6 |
|
T25 |
715 |
|
T27 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8408795 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
83 |
| auto[1] |
6179377 |
1 |
|
|
T24 |
10 |
|
T25 |
1412 |
|
T27 |
87 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1773659 |
1 |
|
|
T24 |
3 |
|
T25 |
374 |
|
T27 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1303162 |
1 |
|
|
T24 |
4 |
|
T25 |
363 |
|
T27 |
23 |
| auto[1] |
auto[1] |
auto[0] |
1792963 |
1 |
|
|
T24 |
1 |
|
T25 |
323 |
|
T27 |
24 |
| auto[1] |
auto[1] |
auto[1] |
1309593 |
1 |
|
|
T24 |
2 |
|
T25 |
352 |
|
T27 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |