Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434960 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6153212 |
1 |
|
|
T24 |
40 |
|
T25 |
1563 |
|
T27 |
137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11996280 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
83 |
| auto[1] |
2591892 |
1 |
|
|
T24 |
10 |
|
T25 |
635 |
|
T27 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8451972 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
65 |
| auto[1] |
6136200 |
1 |
|
|
T24 |
28 |
|
T25 |
1276 |
|
T27 |
114 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1775599 |
1 |
|
|
T24 |
8 |
|
T25 |
261 |
|
T27 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1296935 |
1 |
|
|
T24 |
10 |
|
T25 |
232 |
|
T27 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1768709 |
1 |
|
|
T24 |
10 |
|
T25 |
380 |
|
T27 |
27 |
| auto[1] |
auto[1] |
auto[1] |
1294957 |
1 |
|
|
T25 |
403 |
|
T27 |
50 |
|
T28 |
56341 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |