Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435281 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
62 |
| auto[1] |
6152891 |
1 |
|
|
T24 |
31 |
|
T25 |
1452 |
|
T27 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11969451 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
86 |
| auto[1] |
2618721 |
1 |
|
|
T24 |
7 |
|
T25 |
840 |
|
T27 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8400589 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6187583 |
1 |
|
|
T24 |
24 |
|
T25 |
1588 |
|
T27 |
74 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1794125 |
1 |
|
|
T24 |
8 |
|
T25 |
305 |
|
T27 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1316223 |
1 |
|
|
T24 |
5 |
|
T25 |
325 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1774737 |
1 |
|
|
T24 |
9 |
|
T25 |
443 |
|
T27 |
33 |
| auto[1] |
auto[1] |
auto[1] |
1302498 |
1 |
|
|
T24 |
2 |
|
T25 |
515 |
|
T27 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |