Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453008 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
72 |
| auto[1] |
6135164 |
1 |
|
|
T24 |
21 |
|
T25 |
1075 |
|
T27 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11987830 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
90 |
| auto[1] |
2600342 |
1 |
|
|
T24 |
3 |
|
T25 |
760 |
|
T27 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8463915 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
86 |
| auto[1] |
6124257 |
1 |
|
|
T24 |
7 |
|
T25 |
1534 |
|
T27 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1767443 |
1 |
|
|
T24 |
2 |
|
T25 |
456 |
|
T27 |
25 |
| auto[1] |
auto[0] |
auto[1] |
1302618 |
1 |
|
|
T25 |
483 |
|
T27 |
19 |
|
T28 |
55716 |
| auto[1] |
auto[1] |
auto[0] |
1756472 |
1 |
|
|
T24 |
2 |
|
T25 |
318 |
|
T27 |
28 |
| auto[1] |
auto[1] |
auto[1] |
1297724 |
1 |
|
|
T24 |
3 |
|
T25 |
277 |
|
T27 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |