Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8398974 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6189198 |
1 |
|
|
T24 |
24 |
|
T25 |
1329 |
|
T27 |
95 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11982132 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
73 |
| auto[1] |
2606040 |
1 |
|
|
T24 |
20 |
|
T25 |
587 |
|
T27 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426060 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
66 |
| auto[1] |
6162112 |
1 |
|
|
T24 |
27 |
|
T25 |
1155 |
|
T27 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1775200 |
1 |
|
|
T24 |
5 |
|
T25 |
241 |
|
T27 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1302755 |
1 |
|
|
T24 |
13 |
|
T25 |
239 |
|
T27 |
22 |
| auto[1] |
auto[1] |
auto[0] |
1780872 |
1 |
|
|
T24 |
2 |
|
T25 |
327 |
|
T27 |
22 |
| auto[1] |
auto[1] |
auto[1] |
1303285 |
1 |
|
|
T24 |
7 |
|
T25 |
348 |
|
T27 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |