Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8377069 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
60 |
| auto[1] |
6211103 |
1 |
|
|
T24 |
33 |
|
T25 |
1463 |
|
T27 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11986032 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
79 |
| auto[1] |
2602140 |
1 |
|
|
T24 |
14 |
|
T25 |
606 |
|
T27 |
75 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8446263 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
66 |
| auto[1] |
6141909 |
1 |
|
|
T24 |
27 |
|
T25 |
1233 |
|
T27 |
108 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1758107 |
1 |
|
|
T24 |
10 |
|
T25 |
256 |
|
T27 |
22 |
| auto[1] |
auto[0] |
auto[1] |
1293978 |
1 |
|
|
T24 |
6 |
|
T25 |
240 |
|
T27 |
43 |
| auto[1] |
auto[1] |
auto[0] |
1781662 |
1 |
|
|
T24 |
3 |
|
T25 |
371 |
|
T27 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1308162 |
1 |
|
|
T24 |
8 |
|
T25 |
366 |
|
T27 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |