Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437801 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
85 |
| auto[1] |
6150371 |
1 |
|
|
T24 |
8 |
|
T25 |
1101 |
|
T27 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11961735 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
85 |
| auto[1] |
2626437 |
1 |
|
|
T24 |
8 |
|
T25 |
596 |
|
T27 |
30 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8389899 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
72 |
| auto[1] |
6198273 |
1 |
|
|
T24 |
21 |
|
T25 |
1172 |
|
T27 |
92 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1795226 |
1 |
|
|
T24 |
13 |
|
T25 |
322 |
|
T27 |
31 |
| auto[1] |
auto[0] |
auto[1] |
1322280 |
1 |
|
|
T24 |
5 |
|
T25 |
322 |
|
T27 |
21 |
| auto[1] |
auto[1] |
auto[0] |
1776610 |
1 |
|
|
T25 |
254 |
|
T27 |
31 |
|
T28 |
90912 |
| auto[1] |
auto[1] |
auto[1] |
1304157 |
1 |
|
|
T24 |
3 |
|
T25 |
274 |
|
T27 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |