Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8445615 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
82 |
| auto[1] |
6142557 |
1 |
|
|
T24 |
11 |
|
T25 |
1386 |
|
T27 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11996552 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
78 |
| auto[1] |
2591620 |
1 |
|
|
T24 |
15 |
|
T25 |
634 |
|
T27 |
74 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8459310 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
60 |
| auto[1] |
6128862 |
1 |
|
|
T24 |
33 |
|
T25 |
1289 |
|
T27 |
116 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1778570 |
1 |
|
|
T24 |
16 |
|
T25 |
304 |
|
T27 |
35 |
| auto[1] |
auto[0] |
auto[1] |
1301955 |
1 |
|
|
T24 |
15 |
|
T25 |
332 |
|
T27 |
39 |
| auto[1] |
auto[1] |
auto[0] |
1758672 |
1 |
|
|
T24 |
2 |
|
T25 |
351 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1289665 |
1 |
|
|
T25 |
302 |
|
T27 |
35 |
|
T28 |
56243 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |