Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8427721 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
59 |
| auto[1] |
6160451 |
1 |
|
|
T24 |
34 |
|
T25 |
1262 |
|
T27 |
127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11975584 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
80 |
| auto[1] |
2612588 |
1 |
|
|
T24 |
13 |
|
T25 |
515 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8416750 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
71 |
| auto[1] |
6171422 |
1 |
|
|
T24 |
22 |
|
T25 |
1042 |
|
T27 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1780763 |
1 |
|
|
T24 |
3 |
|
T25 |
254 |
|
T27 |
20 |
| auto[1] |
auto[0] |
auto[1] |
1308155 |
1 |
|
|
T24 |
3 |
|
T25 |
239 |
|
T28 |
55614 |
| auto[1] |
auto[1] |
auto[0] |
1778071 |
1 |
|
|
T24 |
6 |
|
T25 |
273 |
|
T27 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1304433 |
1 |
|
|
T24 |
10 |
|
T25 |
276 |
|
T27 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |