Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440820 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
78 |
| auto[1] |
6147352 |
1 |
|
|
T24 |
15 |
|
T25 |
1235 |
|
T27 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11981982 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
78 |
| auto[1] |
2606190 |
1 |
|
|
T24 |
15 |
|
T25 |
605 |
|
T27 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426960 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6161212 |
1 |
|
|
T24 |
40 |
|
T25 |
1132 |
|
T27 |
131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1792392 |
1 |
|
|
T24 |
18 |
|
T25 |
261 |
|
T27 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1313540 |
1 |
|
|
T24 |
11 |
|
T25 |
303 |
|
T27 |
33 |
| auto[1] |
auto[1] |
auto[0] |
1762630 |
1 |
|
|
T24 |
7 |
|
T25 |
266 |
|
T27 |
35 |
| auto[1] |
auto[1] |
auto[1] |
1292650 |
1 |
|
|
T24 |
4 |
|
T25 |
302 |
|
T27 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |