Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426279 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
64 |
| auto[1] |
6161893 |
1 |
|
|
T24 |
29 |
|
T25 |
1042 |
|
T27 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13798469 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
789703 |
1 |
|
|
T25 |
232 |
|
T27 |
4 |
|
T28 |
38284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8407767 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
75 |
| auto[1] |
6180405 |
1 |
|
|
T24 |
18 |
|
T25 |
1123 |
|
T27 |
143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2705137 |
1 |
|
|
T24 |
8 |
|
T25 |
562 |
|
T27 |
76 |
| auto[1] |
auto[0] |
auto[1] |
396880 |
1 |
|
|
T25 |
138 |
|
T27 |
3 |
|
T28 |
18901 |
| auto[1] |
auto[1] |
auto[0] |
2685565 |
1 |
|
|
T24 |
10 |
|
T25 |
329 |
|
T27 |
63 |
| auto[1] |
auto[1] |
auto[1] |
392823 |
1 |
|
|
T25 |
94 |
|
T27 |
1 |
|
T28 |
19383 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |