Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462977 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
68 |
| auto[1] |
6125195 |
1 |
|
|
T24 |
25 |
|
T25 |
1379 |
|
T27 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11975626 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
83 |
| auto[1] |
2612546 |
1 |
|
|
T24 |
10 |
|
T25 |
725 |
|
T27 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8402079 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
72 |
| auto[1] |
6186093 |
1 |
|
|
T24 |
21 |
|
T25 |
1381 |
|
T27 |
72 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1802860 |
1 |
|
|
T24 |
11 |
|
T25 |
296 |
|
T27 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1316813 |
1 |
|
|
T24 |
3 |
|
T25 |
307 |
|
T27 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1770687 |
1 |
|
|
T25 |
360 |
|
T27 |
26 |
|
T28 |
95709 |
| auto[1] |
auto[1] |
auto[1] |
1295733 |
1 |
|
|
T24 |
7 |
|
T25 |
418 |
|
T27 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |