Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437543 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6150629 |
1 |
|
|
T24 |
40 |
|
T25 |
1006 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11971027 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
82 |
| auto[1] |
2617145 |
1 |
|
|
T24 |
11 |
|
T25 |
666 |
|
T27 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8405215 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
75 |
| auto[1] |
6182957 |
1 |
|
|
T24 |
18 |
|
T25 |
1330 |
|
T27 |
86 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1783771 |
1 |
|
|
T24 |
7 |
|
T25 |
481 |
|
T27 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1309200 |
1 |
|
|
T24 |
8 |
|
T25 |
493 |
|
T27 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1782041 |
1 |
|
|
T25 |
183 |
|
T27 |
17 |
|
T28 |
95546 |
| auto[1] |
auto[1] |
auto[1] |
1307945 |
1 |
|
|
T24 |
3 |
|
T25 |
173 |
|
T27 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |