Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8388631 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
75 |
| auto[1] |
6199541 |
1 |
|
|
T24 |
18 |
|
T25 |
1169 |
|
T27 |
86 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11990831 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
2597341 |
1 |
|
|
T24 |
23 |
|
T25 |
609 |
|
T27 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8449653 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
44 |
| auto[1] |
6138519 |
1 |
|
|
T24 |
49 |
|
T25 |
1251 |
|
T27 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1765580 |
1 |
|
|
T24 |
22 |
|
T25 |
416 |
|
T27 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1296174 |
1 |
|
|
T24 |
15 |
|
T25 |
348 |
|
T27 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1775598 |
1 |
|
|
T24 |
4 |
|
T25 |
226 |
|
T27 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1301167 |
1 |
|
|
T24 |
8 |
|
T25 |
261 |
|
T27 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |