Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403108 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
81 |
| auto[1] |
6185064 |
1 |
|
|
T24 |
12 |
|
T25 |
1002 |
|
T27 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13793428 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
794744 |
1 |
|
|
T25 |
229 |
|
T27 |
4 |
|
T28 |
37772 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8374328 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
6213844 |
1 |
|
|
T24 |
23 |
|
T25 |
1138 |
|
T27 |
124 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2701744 |
1 |
|
|
T24 |
20 |
|
T25 |
509 |
|
T27 |
58 |
| auto[1] |
auto[0] |
auto[1] |
395730 |
1 |
|
|
T25 |
132 |
|
T27 |
1 |
|
T28 |
18683 |
| auto[1] |
auto[1] |
auto[0] |
2717356 |
1 |
|
|
T24 |
3 |
|
T25 |
400 |
|
T27 |
62 |
| auto[1] |
auto[1] |
auto[1] |
399014 |
1 |
|
|
T25 |
97 |
|
T27 |
3 |
|
T28 |
19089 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |