Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403932 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6184240 |
1 |
|
|
T24 |
40 |
|
T25 |
1373 |
|
T27 |
108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801459 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
786713 |
1 |
|
|
T25 |
219 |
|
T27 |
7 |
|
T28 |
37659 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426983 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
63 |
| auto[1] |
6161189 |
1 |
|
|
T24 |
30 |
|
T25 |
1163 |
|
T27 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2689742 |
1 |
|
|
T24 |
17 |
|
T25 |
476 |
|
T27 |
37 |
| auto[1] |
auto[0] |
auto[1] |
394028 |
1 |
|
|
T25 |
114 |
|
T27 |
3 |
|
T28 |
18595 |
| auto[1] |
auto[1] |
auto[0] |
2684734 |
1 |
|
|
T24 |
13 |
|
T25 |
468 |
|
T27 |
52 |
| auto[1] |
auto[1] |
auto[1] |
392685 |
1 |
|
|
T25 |
105 |
|
T27 |
4 |
|
T28 |
19064 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |