Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442960 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6145212 |
1 |
|
|
T24 |
40 |
|
T25 |
1249 |
|
T27 |
130 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13797604 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
790568 |
1 |
|
|
T24 |
1 |
|
T25 |
208 |
|
T27 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8410391 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
58 |
| auto[1] |
6177781 |
1 |
|
|
T24 |
35 |
|
T25 |
970 |
|
T27 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2704920 |
1 |
|
|
T24 |
15 |
|
T25 |
359 |
|
T27 |
25 |
| auto[1] |
auto[0] |
auto[1] |
396549 |
1 |
|
|
T25 |
90 |
|
T28 |
19313 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2682293 |
1 |
|
|
T24 |
19 |
|
T25 |
403 |
|
T27 |
71 |
| auto[1] |
auto[1] |
auto[1] |
394019 |
1 |
|
|
T24 |
1 |
|
T25 |
118 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |