Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8420438 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
54 |
| auto[1] |
6167734 |
1 |
|
|
T24 |
39 |
|
T25 |
1057 |
|
T27 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13798020 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
790152 |
1 |
|
|
T25 |
253 |
|
T27 |
6 |
|
T28 |
39035 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8397210 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
59 |
| auto[1] |
6190962 |
1 |
|
|
T24 |
34 |
|
T25 |
1313 |
|
T27 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2707236 |
1 |
|
|
T24 |
17 |
|
T25 |
611 |
|
T27 |
55 |
| auto[1] |
auto[0] |
auto[1] |
396084 |
1 |
|
|
T25 |
150 |
|
T27 |
3 |
|
T28 |
18286 |
| auto[1] |
auto[1] |
auto[0] |
2693574 |
1 |
|
|
T24 |
17 |
|
T25 |
449 |
|
T27 |
58 |
| auto[1] |
auto[1] |
auto[1] |
394068 |
1 |
|
|
T25 |
103 |
|
T27 |
3 |
|
T28 |
20749 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |