Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434311 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
60 |
| auto[1] |
6153861 |
1 |
|
|
T24 |
33 |
|
T25 |
1261 |
|
T27 |
116 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13799807 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
91 |
| auto[1] |
788365 |
1 |
|
|
T24 |
2 |
|
T25 |
283 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8412200 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
6175972 |
1 |
|
|
T24 |
23 |
|
T25 |
1441 |
|
T27 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2706848 |
1 |
|
|
T24 |
16 |
|
T25 |
605 |
|
T27 |
25 |
| auto[1] |
auto[0] |
auto[1] |
397165 |
1 |
|
|
T24 |
1 |
|
T25 |
146 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2680759 |
1 |
|
|
T24 |
5 |
|
T25 |
553 |
|
T27 |
30 |
| auto[1] |
auto[1] |
auto[1] |
391200 |
1 |
|
|
T24 |
1 |
|
T25 |
137 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |