Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403420 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
57 |
| auto[1] |
6184752 |
1 |
|
|
T24 |
36 |
|
T25 |
1256 |
|
T27 |
158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13804365 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
783807 |
1 |
|
|
T25 |
234 |
|
T27 |
2 |
|
T28 |
38016 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437387 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
6150785 |
1 |
|
|
T24 |
23 |
|
T25 |
1237 |
|
T27 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2675320 |
1 |
|
|
T24 |
11 |
|
T25 |
584 |
|
T27 |
8 |
| auto[1] |
auto[0] |
auto[1] |
389474 |
1 |
|
|
T25 |
136 |
|
T27 |
1 |
|
T28 |
18636 |
| auto[1] |
auto[1] |
auto[0] |
2691658 |
1 |
|
|
T24 |
12 |
|
T25 |
419 |
|
T27 |
46 |
| auto[1] |
auto[1] |
auto[1] |
394333 |
1 |
|
|
T25 |
98 |
|
T27 |
1 |
|
T28 |
19380 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |