Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
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T765 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1942803430 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 568680352 ps
T766 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2516518403 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:01 PM PDT 24 65881125 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2604885536 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 23894413 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2156378942 Mar 12 12:30:16 PM PDT 24 Mar 12 12:30:18 PM PDT 24 70141374 ps
T769 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2306829115 Mar 12 12:30:36 PM PDT 24 Mar 12 12:30:37 PM PDT 24 22244063 ps
T770 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1447710354 Mar 12 12:30:10 PM PDT 24 Mar 12 12:30:10 PM PDT 24 51406754 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1494562583 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 144807549 ps
T772 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1524650515 Mar 12 12:30:11 PM PDT 24 Mar 12 12:30:13 PM PDT 24 135366221 ps
T773 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1947957432 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:10 PM PDT 24 66791525 ps
T774 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.43345829 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 27891199 ps
T775 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1507640855 Mar 12 12:30:26 PM PDT 24 Mar 12 12:30:27 PM PDT 24 210555789 ps
T43 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1252136118 Mar 12 12:30:23 PM PDT 24 Mar 12 12:30:24 PM PDT 24 49544417 ps
T776 /workspace/coverage/cover_reg_top/27.gpio_intr_test.250867681 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:19 PM PDT 24 26950533 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1105062160 Mar 12 12:30:20 PM PDT 24 Mar 12 12:30:21 PM PDT 24 15335624 ps
T778 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.621214639 Mar 12 12:30:27 PM PDT 24 Mar 12 12:30:27 PM PDT 24 55772419 ps
T779 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3317949622 Mar 12 12:29:58 PM PDT 24 Mar 12 12:30:00 PM PDT 24 1678414969 ps
T780 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1663289120 Mar 12 12:30:36 PM PDT 24 Mar 12 12:30:37 PM PDT 24 30284035 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2700152965 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 33243883 ps
T782 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3579707626 Mar 12 12:30:01 PM PDT 24 Mar 12 12:30:02 PM PDT 24 119131124 ps
T783 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2145810605 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 68552843 ps
T79 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1666343487 Mar 12 12:30:15 PM PDT 24 Mar 12 12:30:16 PM PDT 24 19805120 ps
T784 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3240002675 Mar 12 12:30:19 PM PDT 24 Mar 12 12:30:20 PM PDT 24 72761445 ps
T785 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1111372875 Mar 12 12:30:24 PM PDT 24 Mar 12 12:30:25 PM PDT 24 13724488 ps
T47 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1295739323 Mar 12 12:30:03 PM PDT 24 Mar 12 12:30:04 PM PDT 24 214200320 ps
T786 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.714994986 Mar 12 12:30:08 PM PDT 24 Mar 12 12:30:08 PM PDT 24 52227985 ps
T787 /workspace/coverage/cover_reg_top/26.gpio_intr_test.4250736593 Mar 12 12:30:24 PM PDT 24 Mar 12 12:30:25 PM PDT 24 15987288 ps
T48 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.971183281 Mar 12 12:30:31 PM PDT 24 Mar 12 12:30:32 PM PDT 24 318839172 ps
T788 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2396931632 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:16 PM PDT 24 293206887 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3858550415 Mar 12 12:30:10 PM PDT 24 Mar 12 12:30:13 PM PDT 24 842012219 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1382400333 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:20 PM PDT 24 16736833 ps
T791 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2862109548 Mar 12 12:30:25 PM PDT 24 Mar 12 12:30:26 PM PDT 24 31486943 ps
T792 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2856904965 Mar 12 12:30:26 PM PDT 24 Mar 12 12:30:27 PM PDT 24 42357266 ps
T80 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1715291133 Mar 12 12:30:11 PM PDT 24 Mar 12 12:30:12 PM PDT 24 123428110 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4246859624 Mar 12 12:30:10 PM PDT 24 Mar 12 12:30:12 PM PDT 24 107929606 ps
T794 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4108377407 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:02 PM PDT 24 72268990 ps
T795 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2186359507 Mar 12 12:30:19 PM PDT 24 Mar 12 12:30:19 PM PDT 24 23187229 ps
T796 /workspace/coverage/cover_reg_top/21.gpio_intr_test.92624610 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:09 PM PDT 24 16157493 ps
T797 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.41208920 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 153231732 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3519443364 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 12748627 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.665010112 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 32520575 ps
T800 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2408161482 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:20 PM PDT 24 69491163 ps
T44 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3698898858 Mar 12 12:30:26 PM PDT 24 Mar 12 12:30:27 PM PDT 24 179983824 ps
T801 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3621981833 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:58 PM PDT 24 12222611 ps
T81 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.666220057 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:59 PM PDT 24 72674974 ps
T802 /workspace/coverage/cover_reg_top/49.gpio_intr_test.526650377 Mar 12 12:30:41 PM PDT 24 Mar 12 12:30:42 PM PDT 24 16237503 ps
T803 /workspace/coverage/cover_reg_top/25.gpio_intr_test.187617336 Mar 12 12:30:35 PM PDT 24 Mar 12 12:30:35 PM PDT 24 38185447 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2570266602 Mar 12 12:30:40 PM PDT 24 Mar 12 12:30:42 PM PDT 24 55575087 ps
T805 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2957488930 Mar 12 12:30:12 PM PDT 24 Mar 12 12:30:13 PM PDT 24 96200813 ps
T806 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.659342448 Mar 12 12:30:22 PM PDT 24 Mar 12 12:30:23 PM PDT 24 20685497 ps
T95 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.824301809 Mar 12 12:30:15 PM PDT 24 Mar 12 12:30:16 PM PDT 24 288033589 ps
T807 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2217916683 Mar 12 12:30:19 PM PDT 24 Mar 12 12:30:21 PM PDT 24 15977674 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3414832798 Mar 12 12:29:59 PM PDT 24 Mar 12 12:30:00 PM PDT 24 49514317 ps
T809 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1506901161 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:10 PM PDT 24 720407063 ps
T810 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3003018442 Mar 12 12:30:25 PM PDT 24 Mar 12 12:30:25 PM PDT 24 14729609 ps
T811 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1872267003 Mar 12 12:30:37 PM PDT 24 Mar 12 12:30:38 PM PDT 24 44605829 ps
T82 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2966040120 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:56 PM PDT 24 63161755 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2052164919 Mar 12 12:30:19 PM PDT 24 Mar 12 12:30:20 PM PDT 24 48267775 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3482501913 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 93053493 ps
T814 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1453410167 Mar 12 12:30:15 PM PDT 24 Mar 12 12:30:15 PM PDT 24 15555688 ps
T815 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4108818447 Mar 12 12:30:28 PM PDT 24 Mar 12 12:30:30 PM PDT 24 93701608 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3723893640 Mar 12 12:30:21 PM PDT 24 Mar 12 12:30:22 PM PDT 24 79792908 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1239890920 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:18 PM PDT 24 108770427 ps
T818 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.539187151 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:16 PM PDT 24 90524978 ps
T819 /workspace/coverage/cover_reg_top/35.gpio_intr_test.589373269 Mar 12 12:30:22 PM PDT 24 Mar 12 12:30:22 PM PDT 24 130068346 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3311942922 Mar 12 12:30:16 PM PDT 24 Mar 12 12:30:17 PM PDT 24 270096274 ps
T821 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.97393408 Mar 12 12:30:32 PM PDT 24 Mar 12 12:30:35 PM PDT 24 345849450 ps
T86 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1119365851 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:10 PM PDT 24 32773415 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_intr_test.787065694 Mar 12 12:30:28 PM PDT 24 Mar 12 12:30:29 PM PDT 24 40398717 ps
T823 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.564181820 Mar 12 12:30:21 PM PDT 24 Mar 12 12:30:22 PM PDT 24 135567296 ps
T824 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.269820319 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:19 PM PDT 24 50141552 ps
T83 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2322463397 Mar 12 12:30:05 PM PDT 24 Mar 12 12:30:06 PM PDT 24 14064250 ps
T825 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1218258095 Mar 12 12:30:05 PM PDT 24 Mar 12 12:30:06 PM PDT 24 22807398 ps
T826 /workspace/coverage/cover_reg_top/42.gpio_intr_test.62130989 Mar 12 12:30:40 PM PDT 24 Mar 12 12:30:40 PM PDT 24 15657002 ps
T827 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1002088625 Mar 12 12:30:11 PM PDT 24 Mar 12 12:30:12 PM PDT 24 173578902 ps
T828 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1617070471 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:58 PM PDT 24 123403918 ps
T829 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3294077614 Mar 12 12:30:20 PM PDT 24 Mar 12 12:30:21 PM PDT 24 35977644 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2645494614 Mar 12 12:30:11 PM PDT 24 Mar 12 12:30:11 PM PDT 24 64732767 ps
T830 /workspace/coverage/cover_reg_top/34.gpio_intr_test.7314998 Mar 12 12:30:24 PM PDT 24 Mar 12 12:30:25 PM PDT 24 26280254 ps
T831 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.200417764 Mar 12 12:30:04 PM PDT 24 Mar 12 12:30:04 PM PDT 24 45837487 ps
T85 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4270720666 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:01 PM PDT 24 62682491 ps
T832 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3755235288 Mar 12 12:30:04 PM PDT 24 Mar 12 12:30:04 PM PDT 24 39190844 ps
T833 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1176908497 Mar 12 12:30:26 PM PDT 24 Mar 12 12:30:26 PM PDT 24 51937897 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3728637996 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 52005727 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3492349045 Mar 12 12:29:59 PM PDT 24 Mar 12 12:30:00 PM PDT 24 40063723 ps
T836 /workspace/coverage/cover_reg_top/29.gpio_intr_test.801175520 Mar 12 12:30:18 PM PDT 24 Mar 12 12:30:20 PM PDT 24 19500234 ps
T837 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2101454276 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:10 PM PDT 24 31597049 ps
T838 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2869060277 Mar 12 12:30:34 PM PDT 24 Mar 12 12:30:34 PM PDT 24 15083534 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1414796316 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:01 PM PDT 24 44498660 ps
T840 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3907901361 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:59 PM PDT 24 22457685 ps
T841 /workspace/coverage/cover_reg_top/22.gpio_intr_test.496918193 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 15204293 ps
T87 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.525019257 Mar 12 12:29:57 PM PDT 24 Mar 12 12:30:00 PM PDT 24 231927901 ps
T842 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1815825610 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:57 PM PDT 24 334018413 ps
T843 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3616220358 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:54 PM PDT 24 180514043 ps
T844 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3276621309 Mar 12 12:30:10 PM PDT 24 Mar 12 12:30:12 PM PDT 24 59807508 ps
T845 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1394433403 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:51 PM PDT 24 33919628 ps
T846 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4218724181 Mar 12 12:30:41 PM PDT 24 Mar 12 12:30:43 PM PDT 24 215521961 ps
T847 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2527260046 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:49 PM PDT 24 31692308 ps
T848 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.312451911 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 143357173 ps
T849 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1166755718 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 32016635 ps
T850 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.382026826 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 172858731 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.580936511 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:58 PM PDT 24 376785256 ps
T852 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3665800883 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:03 PM PDT 24 75729507 ps
T853 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1964683655 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:58 PM PDT 24 147831476 ps
T854 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206863393 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:59 PM PDT 24 166770767 ps
T855 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1474004895 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:01 PM PDT 24 176600123 ps
T856 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844819308 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:56 PM PDT 24 46739732 ps
T857 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813570962 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:48 PM PDT 24 44816442 ps
T858 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373565308 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:55 PM PDT 24 77000322 ps
T859 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.123298249 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 45124972 ps
T860 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3259858010 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 46606268 ps
T861 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1692100840 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 76667773 ps
T862 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474654841 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:57 PM PDT 24 797463959 ps
T863 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2561141549 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:56 PM PDT 24 136852826 ps
T864 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410471800 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:52 PM PDT 24 108466704 ps
T865 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1982343632 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 133665709 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2220479814 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:53 PM PDT 24 236434594 ps
T867 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1429180453 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 763104732 ps
T868 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4267270657 Mar 12 12:30:08 PM PDT 24 Mar 12 12:30:08 PM PDT 24 36359065 ps
T869 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2729928562 Mar 12 12:29:42 PM PDT 24 Mar 12 12:29:43 PM PDT 24 182556732 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2861733553 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 89919302 ps
T871 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111962676 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 210128191 ps
T872 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3278992070 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 109332987 ps
T873 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.974516179 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:56 PM PDT 24 120493822 ps
T874 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1878567635 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 46097649 ps
T875 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905450156 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:57 PM PDT 24 478341367 ps
T876 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49312568 Mar 12 12:29:43 PM PDT 24 Mar 12 12:29:45 PM PDT 24 129345029 ps
T877 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1208304133 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:58 PM PDT 24 48235867 ps
T878 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3622026787 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 153342830 ps
T879 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3554119094 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 60156783 ps
T880 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4188587915 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:55 PM PDT 24 360830780 ps
T881 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2029521737 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 40288477 ps
T882 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544385810 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 68358132 ps
T883 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2227424798 Mar 12 12:30:07 PM PDT 24 Mar 12 12:30:08 PM PDT 24 134742899 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2661514475 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:15 PM PDT 24 57769348 ps
T885 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223252838 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:58 PM PDT 24 120943970 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2049926915 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:56 PM PDT 24 66947413 ps
T887 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.29272742 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 128130775 ps
T888 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1658890334 Mar 12 12:29:58 PM PDT 24 Mar 12 12:29:59 PM PDT 24 79476688 ps
T889 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329675047 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 849002450 ps
T890 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1201532420 Mar 12 12:30:02 PM PDT 24 Mar 12 12:30:04 PM PDT 24 85687115 ps
T891 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3063269533 Mar 12 12:30:01 PM PDT 24 Mar 12 12:30:03 PM PDT 24 243906912 ps
T892 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1375426080 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:48 PM PDT 24 565060688 ps
T893 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2878531707 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 65336504 ps
T894 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.636317162 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 169600112 ps
T895 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3564847873 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:59 PM PDT 24 206283748 ps
T896 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3212624915 Mar 12 12:29:58 PM PDT 24 Mar 12 12:30:00 PM PDT 24 258651272 ps
T897 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.172288702 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:51 PM PDT 24 305385783 ps
T898 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1476910847 Mar 12 12:29:49 PM PDT 24 Mar 12 12:29:50 PM PDT 24 36730769 ps
T899 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501944573 Mar 12 12:30:10 PM PDT 24 Mar 12 12:30:12 PM PDT 24 400425893 ps
T900 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011131595 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:02 PM PDT 24 64040399 ps
T901 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2970461254 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 165075837 ps
T902 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639802391 Mar 12 12:29:54 PM PDT 24 Mar 12 12:29:55 PM PDT 24 26816778 ps
T903 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.166942123 Mar 12 12:29:57 PM PDT 24 Mar 12 12:29:59 PM PDT 24 285366037 ps
T904 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1262006269 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:58 PM PDT 24 456587014 ps
T905 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3223128129 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:57 PM PDT 24 83571973 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1693104967 Mar 12 12:29:48 PM PDT 24 Mar 12 12:29:50 PM PDT 24 147088325 ps
T907 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4083472951 Mar 12 12:29:39 PM PDT 24 Mar 12 12:29:40 PM PDT 24 144404872 ps
T908 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4014224478 Mar 12 12:29:46 PM PDT 24 Mar 12 12:29:48 PM PDT 24 171547781 ps
T909 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3721263478 Mar 12 12:30:16 PM PDT 24 Mar 12 12:30:17 PM PDT 24 70554137 ps
T910 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4062561075 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 81218883 ps
T911 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2752532443 Mar 12 12:29:58 PM PDT 24 Mar 12 12:30:00 PM PDT 24 185392240 ps
T912 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2051634571 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:56 PM PDT 24 53547647 ps
T913 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2455465321 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 155716380 ps
T914 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1635715470 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 94294823 ps
T915 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2514396486 Mar 12 12:29:47 PM PDT 24 Mar 12 12:29:49 PM PDT 24 101888582 ps
T916 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.207905451 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 306519423 ps
T917 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1865831645 Mar 12 12:30:01 PM PDT 24 Mar 12 12:30:08 PM PDT 24 153748919 ps
T918 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2926982437 Mar 12 12:29:39 PM PDT 24 Mar 12 12:29:40 PM PDT 24 47509012 ps
T919 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.253277521 Mar 12 12:30:01 PM PDT 24 Mar 12 12:30:03 PM PDT 24 78815556 ps
T920 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1220622667 Mar 12 12:30:22 PM PDT 24 Mar 12 12:30:24 PM PDT 24 35639332 ps
T921 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2857578891 Mar 12 12:29:57 PM PDT 24 Mar 12 12:30:03 PM PDT 24 175839540 ps
T922 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151658853 Mar 12 12:29:43 PM PDT 24 Mar 12 12:29:44 PM PDT 24 174547247 ps
T923 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3137865611 Mar 12 12:29:53 PM PDT 24 Mar 12 12:29:54 PM PDT 24 40759346 ps
T924 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3593417886 Mar 12 12:29:55 PM PDT 24 Mar 12 12:29:57 PM PDT 24 45014000 ps
T925 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136781889 Mar 12 12:30:00 PM PDT 24 Mar 12 12:30:02 PM PDT 24 68809021 ps
T926 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.90686239 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:52 PM PDT 24 35898533 ps
T927 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986267948 Mar 12 12:29:56 PM PDT 24 Mar 12 12:29:57 PM PDT 24 59376632 ps
T928 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3070003989 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 48493003 ps
T929 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.269951859 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 136149554 ps
T930 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1927926496 Mar 12 12:30:06 PM PDT 24 Mar 12 12:30:08 PM PDT 24 155190840 ps
T931 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3315490962 Mar 12 12:30:03 PM PDT 24 Mar 12 12:30:04 PM PDT 24 352615716 ps
T932 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3126696186 Mar 12 12:30:14 PM PDT 24 Mar 12 12:30:15 PM PDT 24 204932881 ps
T933 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.516792330 Mar 12 12:30:15 PM PDT 24 Mar 12 12:30:17 PM PDT 24 254261944 ps
T934 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3872485925 Mar 12 12:29:44 PM PDT 24 Mar 12 12:29:46 PM PDT 24 57390344 ps
T935 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.399357767 Mar 12 12:30:03 PM PDT 24 Mar 12 12:30:05 PM PDT 24 80093983 ps
T936 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4047725756 Mar 12 12:29:51 PM PDT 24 Mar 12 12:29:53 PM PDT 24 29618681 ps
T937 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322484093 Mar 12 12:29:50 PM PDT 24 Mar 12 12:29:52 PM PDT 24 38904830 ps
T938 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261339554 Mar 12 12:30:13 PM PDT 24 Mar 12 12:30:14 PM PDT 24 37746664 ps
T939 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2240017588 Mar 12 12:29:40 PM PDT 24 Mar 12 12:29:42 PM PDT 24 35197268 ps
T940 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3676511196 Mar 12 12:29:52 PM PDT 24 Mar 12 12:29:54 PM PDT 24 80620233 ps
T941 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3179931846 Mar 12 12:30:09 PM PDT 24 Mar 12 12:30:11 PM PDT 24 96988664 ps

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1250886340
Short name T28
Test name
Test status
Simulation time 229779721765 ps
CPU time 1519.96 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 01:19:49 PM PDT 24
Peak memory 197800 kb
Host smart-8d5d4025-d600-4f10-b75a-d13533379292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1250886340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1250886340
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.134110216
Short name T101
Test name
Test status
Simulation time 77578075 ps
CPU time 3.04 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 198176 kb
Host smart-0e1b8b97-eaa5-49f9-898f-838d41465bae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134110216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.134110216
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.97499996
Short name T37
Test name
Test status
Simulation time 90152581 ps
CPU time 0.95 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 214892 kb
Host smart-0a1f0ffa-b7aa-48e7-a980-9141b7a870df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97499996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.97499996
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.623045504
Short name T2
Test name
Test status
Simulation time 3803904446 ps
CPU time 4.61 seconds
Started Mar 12 12:53:32 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 198228 kb
Host smart-d754e5f7-70a6-4611-b17e-5704a88af793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623045504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.623045504
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1107074371
Short name T72
Test name
Test status
Simulation time 148587184 ps
CPU time 2.14 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 196808 kb
Host smart-516451ea-73ba-49d5-a136-90f403f945f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107074371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1107074371
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.430513566
Short name T42
Test name
Test status
Simulation time 501206132 ps
CPU time 1.15 seconds
Started Mar 12 12:30:31 PM PDT 24
Finished Mar 12 12:30:32 PM PDT 24
Peak memory 198132 kb
Host smart-b5d073df-b4a2-4181-a8e0-b7eea91ca6af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430513566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.430513566
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2023963082
Short name T26
Test name
Test status
Simulation time 29999370 ps
CPU time 0.56 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 194248 kb
Host smart-edfbe5a6-4a25-49e8-9d3a-0a5de9206846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023963082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2023963082
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1895124744
Short name T34
Test name
Test status
Simulation time 460759750 ps
CPU time 1.46 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 198060 kb
Host smart-f6c79a4c-c36a-43ec-abdc-015c22f48f90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895124744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1895124744
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2966040120
Short name T82
Test name
Test status
Simulation time 63161755 ps
CPU time 0.91 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 196004 kb
Host smart-910d765b-554f-4b28-a09f-e0871c63049c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966040120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2966040120
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2257074428
Short name T88
Test name
Test status
Simulation time 97366398 ps
CPU time 0.73 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 196624 kb
Host smart-f6f37afe-bf0b-4fce-bf44-c24e38b16599
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257074428 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2257074428
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2784022417
Short name T45
Test name
Test status
Simulation time 50229625 ps
CPU time 0.96 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:02 PM PDT 24
Peak memory 197196 kb
Host smart-048ad37e-0466-4d2b-b899-1636c6b09c65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784022417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2784022417
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1666343487
Short name T79
Test name
Test status
Simulation time 19805120 ps
CPU time 0.67 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 194808 kb
Host smart-d76de105-9402-440e-89fa-364d36b3e644
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666343487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1666343487
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.665010112
Short name T799
Test name
Test status
Simulation time 32520575 ps
CPU time 0.92 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 197888 kb
Host smart-27993b0b-b2f3-4f82-8653-fe82bcdcd167
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665010112 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.665010112
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3907901361
Short name T840
Test name
Test status
Simulation time 22457685 ps
CPU time 0.61 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 194500 kb
Host smart-9e33da95-363d-4d70-9d6a-5d08cda05fa4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907901361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3907901361
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2570266602
Short name T804
Test name
Test status
Simulation time 55575087 ps
CPU time 0.56 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 193704 kb
Host smart-64b94857-727d-45e6-9af0-1fe3d5b15779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570266602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2570266602
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1005124990
Short name T732
Test name
Test status
Simulation time 109663482 ps
CPU time 1.49 seconds
Started Mar 12 12:30:12 PM PDT 24
Finished Mar 12 12:30:13 PM PDT 24
Peak memory 198092 kb
Host smart-04d343be-af37-424a-95b5-3e17c14ba309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005124990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1005124990
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1715291133
Short name T80
Test name
Test status
Simulation time 123428110 ps
CPU time 0.85 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 196776 kb
Host smart-9ab32fe5-90db-4639-baf4-9c5b1b7dfae7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715291133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1715291133
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1909760191
Short name T760
Test name
Test status
Simulation time 1045508448 ps
CPU time 2.36 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 197052 kb
Host smart-e1ff22fb-ce55-468f-98bb-4ff7f3332c25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909760191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1909760191
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2097634186
Short name T68
Test name
Test status
Simulation time 21507178 ps
CPU time 0.65 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 195580 kb
Host smart-d3829421-e265-424d-922e-c789238b9dfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097634186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2097634186
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3492349045
Short name T835
Test name
Test status
Simulation time 40063723 ps
CPU time 0.73 seconds
Started Mar 12 12:29:59 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 197888 kb
Host smart-3769d32e-7147-4506-914f-9afad179274a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492349045 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3492349045
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1617070471
Short name T828
Test name
Test status
Simulation time 123403918 ps
CPU time 0.59 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 195164 kb
Host smart-e29d8b6e-db23-49e7-b451-92108d99afc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617070471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1617070471
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3621981833
Short name T801
Test name
Test status
Simulation time 12222611 ps
CPU time 0.62 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 194432 kb
Host smart-3e017e98-54ed-4263-b1cd-a115485a0ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621981833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3621981833
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2604885536
Short name T767
Test name
Test status
Simulation time 23894413 ps
CPU time 0.72 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:51 PM PDT 24
Peak memory 194716 kb
Host smart-6c9f2a9a-4e0a-44b2-befe-f08c50618325
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604885536 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2604885536
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4246859624
Short name T793
Test name
Test status
Simulation time 107929606 ps
CPU time 1.53 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 198088 kb
Host smart-dc9ff73c-5442-40f4-85e5-6bd8f43fbd01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246859624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4246859624
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2516518403
Short name T766
Test name
Test status
Simulation time 65881125 ps
CPU time 0.72 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:01 PM PDT 24
Peak memory 197908 kb
Host smart-0fd815fa-8aeb-45af-af2f-d3f6efdb292c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516518403 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2516518403
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.858410728
Short name T73
Test name
Test status
Simulation time 24849386 ps
CPU time 0.66 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 195008 kb
Host smart-1b658b21-9f73-492c-98e9-cd6fd6e4c550
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858410728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.858410728
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1453410167
Short name T814
Test name
Test status
Simulation time 15555688 ps
CPU time 0.6 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 193648 kb
Host smart-2c2681d5-bf6a-4219-b532-742b5bcd307f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453410167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1453410167
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2101454276
Short name T837
Test name
Test status
Simulation time 31597049 ps
CPU time 0.93 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 196328 kb
Host smart-c10ab068-2722-4209-91ea-0f18dd184421
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101454276 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2101454276
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1965741204
Short name T742
Test name
Test status
Simulation time 90880382 ps
CPU time 1.26 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 198056 kb
Host smart-9ebbc5bd-0e72-42a9-9732-88d7c2ba6c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965741204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1965741204
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3317949622
Short name T779
Test name
Test status
Simulation time 1678414969 ps
CPU time 1.07 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 197152 kb
Host smart-9e108c41-4b81-486d-9a88-229c2b06af0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317949622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3317949622
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.97393408
Short name T821
Test name
Test status
Simulation time 345849450 ps
CPU time 2.03 seconds
Started Mar 12 12:30:32 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 198128 kb
Host smart-5b520f97-57d7-4f2e-89aa-8ce9efa174f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97393408 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.97393408
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.666220057
Short name T81
Test name
Test status
Simulation time 72674974 ps
CPU time 0.59 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 193548 kb
Host smart-d28643cd-0cb6-409a-ac01-cea363ae1d49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666220057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.666220057
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4216808045
Short name T729
Test name
Test status
Simulation time 12196338 ps
CPU time 0.6 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:19 PM PDT 24
Peak memory 194484 kb
Host smart-6862e3af-3197-453c-8fe7-6098fcf0ba20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216808045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4216808045
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1966832452
Short name T66
Test name
Test status
Simulation time 18014862 ps
CPU time 0.78 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 196932 kb
Host smart-58317cb0-40f0-4708-8957-45d05365b1c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966832452 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1966832452
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1739174911
Short name T718
Test name
Test status
Simulation time 81256834 ps
CPU time 2.87 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:29 PM PDT 24
Peak memory 198068 kb
Host smart-bf33e6f7-b243-428b-bf40-49359e31f094
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739174911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1739174911
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2408161482
Short name T800
Test name
Test status
Simulation time 69491163 ps
CPU time 1.17 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 198080 kb
Host smart-e5387336-5d2c-4dda-8190-3ed640e9b018
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408161482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2408161482
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.564181820
Short name T823
Test name
Test status
Simulation time 135567296 ps
CPU time 1.01 seconds
Started Mar 12 12:30:21 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 197940 kb
Host smart-7522e9a4-314f-4385-8c87-64a53b0925aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564181820 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.564181820
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.503591450
Short name T75
Test name
Test status
Simulation time 12480475 ps
CPU time 0.59 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 194992 kb
Host smart-6ba2dc3e-6ce2-4d5f-816a-0e7735b8fc97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503591450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.503591450
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1176908497
Short name T833
Test name
Test status
Simulation time 51937897 ps
CPU time 0.59 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 193680 kb
Host smart-2f6eab5e-a059-4f28-9ce6-84b40deec64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176908497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1176908497
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1451215470
Short name T92
Test name
Test status
Simulation time 19345741 ps
CPU time 0.82 seconds
Started Mar 12 12:30:29 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 196236 kb
Host smart-c369c2d8-2042-41b5-91f0-9c37b5a73826
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451215470 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1451215470
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2396931632
Short name T788
Test name
Test status
Simulation time 293206887 ps
CPU time 2.74 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 198072 kb
Host smart-a8d0f830-f06e-4958-be58-78b27a9f8fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396931632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2396931632
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1507640855
Short name T775
Test name
Test status
Simulation time 210555789 ps
CPU time 0.91 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 197760 kb
Host smart-17e91889-b856-42af-bf32-fa57cf0e463d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507640855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1507640855
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2268167447
Short name T762
Test name
Test status
Simulation time 25859331 ps
CPU time 1.32 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 198036 kb
Host smart-7f24f64b-1539-4e47-99a7-a3d5e0aee6cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268167447 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2268167447
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2957488930
Short name T805
Test name
Test status
Simulation time 96200813 ps
CPU time 0.6 seconds
Started Mar 12 12:30:12 PM PDT 24
Finished Mar 12 12:30:13 PM PDT 24
Peak memory 193952 kb
Host smart-772e3612-e37d-4859-8bd9-8fbcc0f90c91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957488930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2957488930
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1239890920
Short name T817
Test name
Test status
Simulation time 108770427 ps
CPU time 0.56 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 194216 kb
Host smart-d030e78b-5807-41ed-b571-36fb2b368840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239890920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1239890920
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1500691594
Short name T89
Test name
Test status
Simulation time 55950752 ps
CPU time 0.72 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:23 PM PDT 24
Peak memory 196016 kb
Host smart-a3af344d-fba7-4af9-b473-54eb539745a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500691594 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1500691594
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.41208920
Short name T797
Test name
Test status
Simulation time 153231732 ps
CPU time 1.11 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 197772 kb
Host smart-3a0c73c6-411d-4341-b248-a166865f27ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.41208920
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.971183281
Short name T48
Test name
Test status
Simulation time 318839172 ps
CPU time 1.16 seconds
Started Mar 12 12:30:31 PM PDT 24
Finished Mar 12 12:30:32 PM PDT 24
Peak memory 198084 kb
Host smart-43a640a7-0182-4a47-9200-f62892463a1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971183281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.971183281
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3182506395
Short name T743
Test name
Test status
Simulation time 60177251 ps
CPU time 1.42 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 198172 kb
Host smart-ef2d2fcb-4570-465a-ab56-933da08f0b32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182506395 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3182506395
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1119365851
Short name T86
Test name
Test status
Simulation time 32773415 ps
CPU time 0.58 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 193508 kb
Host smart-a1c4457e-7bca-4936-a738-45484f7955e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119365851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1119365851
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1717185889
Short name T759
Test name
Test status
Simulation time 15073494 ps
CPU time 0.58 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:34 PM PDT 24
Peak memory 193740 kb
Host smart-c7198251-8d56-4801-96c0-15dfd35c24cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717185889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1717185889
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.881213128
Short name T90
Test name
Test status
Simulation time 18271979 ps
CPU time 0.63 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 194428 kb
Host smart-b989aab4-12df-4358-a24d-a1d248c813f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881213128 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.881213128
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4108818447
Short name T815
Test name
Test status
Simulation time 93701608 ps
CPU time 1.86 seconds
Started Mar 12 12:30:28 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 198044 kb
Host smart-dcbddbdc-1e95-45b1-a095-ac63a98734b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108818447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4108818447
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3880356357
Short name T756
Test name
Test status
Simulation time 86394500 ps
CPU time 0.84 seconds
Started Mar 12 12:30:12 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 197176 kb
Host smart-d5215568-ec88-4303-a9a6-e204eaf4149f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880356357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3880356357
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3382795510
Short name T741
Test name
Test status
Simulation time 331914516 ps
CPU time 1.01 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:38 PM PDT 24
Peak memory 197924 kb
Host smart-f9870986-c0dc-492b-a327-523ceeb436da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382795510 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3382795510
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.645183100
Short name T76
Test name
Test status
Simulation time 34032840 ps
CPU time 0.6 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 194884 kb
Host smart-d4f1e578-f5d5-49b7-a24c-89b5f9d6224a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645183100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.645183100
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2079345186
Short name T749
Test name
Test status
Simulation time 30735837 ps
CPU time 0.58 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 194384 kb
Host smart-0846b72f-ff75-4335-9800-a8cfe28eedb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079345186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2079345186
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3707060161
Short name T71
Test name
Test status
Simulation time 48501277 ps
CPU time 0.93 seconds
Started Mar 12 12:30:32 PM PDT 24
Finished Mar 12 12:30:33 PM PDT 24
Peak memory 197812 kb
Host smart-40a12379-ed11-4a8e-91e3-0f415711a464
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707060161 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3707060161
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4282078635
Short name T733
Test name
Test status
Simulation time 475559785 ps
CPU time 1.55 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 197988 kb
Host smart-5f85270b-6ac0-4b3b-9d89-b63191bf938b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282078635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4282078635
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3150325517
Short name T36
Test name
Test status
Simulation time 726324937 ps
CPU time 1.4 seconds
Started Mar 12 12:30:32 PM PDT 24
Finished Mar 12 12:30:33 PM PDT 24
Peak memory 197944 kb
Host smart-95ce5919-e6d9-4671-aa2e-051bb651156f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150325517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3150325517
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3728637996
Short name T834
Test name
Test status
Simulation time 52005727 ps
CPU time 1.37 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 198188 kb
Host smart-6aded021-d151-4bc6-a026-0da8c5e95e23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728637996 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3728637996
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1704487706
Short name T755
Test name
Test status
Simulation time 28773918 ps
CPU time 0.58 seconds
Started Mar 12 12:30:29 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 194500 kb
Host smart-67e94137-73ae-4129-8630-51dbd94f9514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704487706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1704487706
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3240002675
Short name T784
Test name
Test status
Simulation time 72761445 ps
CPU time 0.62 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 193696 kb
Host smart-93642a8e-d80d-4f41-8b12-0c04c528b977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240002675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3240002675
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3479205219
Short name T69
Test name
Test status
Simulation time 160575579 ps
CPU time 0.89 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 196380 kb
Host smart-26b75404-4d61-4f01-b125-9ebd0d026579
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479205219 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3479205219
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2702562703
Short name T753
Test name
Test status
Simulation time 154048344 ps
CPU time 1.59 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 198056 kb
Host smart-50021070-bee8-49c9-bf2a-4c6bd2098b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702562703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2702562703
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3698898858
Short name T44
Test name
Test status
Simulation time 179983824 ps
CPU time 0.88 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 197312 kb
Host smart-1ba95f85-ba7f-4562-b60b-6c74acc19636
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698898858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3698898858
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2862109548
Short name T791
Test name
Test status
Simulation time 31486943 ps
CPU time 0.88 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 197872 kb
Host smart-6532457e-ef42-454a-8f96-f3e4f65b16c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862109548 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2862109548
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.323551138
Short name T67
Test name
Test status
Simulation time 16949323 ps
CPU time 0.63 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 194832 kb
Host smart-a78222f8-8a53-4623-9d24-554bf8c2dfef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323551138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.323551138
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.787065694
Short name T822
Test name
Test status
Simulation time 40398717 ps
CPU time 0.58 seconds
Started Mar 12 12:30:28 PM PDT 24
Finished Mar 12 12:30:29 PM PDT 24
Peak memory 193652 kb
Host smart-fbaf88e1-8f27-49a2-8a53-40c87fcb7b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787065694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.787065694
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.367498225
Short name T74
Test name
Test status
Simulation time 203511503 ps
CPU time 0.81 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 197028 kb
Host smart-8d0411b9-54e2-49e3-bbba-65bb06c3386c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367498225 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.367498225
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.539187151
Short name T818
Test name
Test status
Simulation time 90524978 ps
CPU time 2.1 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 198040 kb
Host smart-a292ec4f-349e-4ebe-99b0-0039f9cf03f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539187151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.539187151
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1252136118
Short name T43
Test name
Test status
Simulation time 49544417 ps
CPU time 0.89 seconds
Started Mar 12 12:30:23 PM PDT 24
Finished Mar 12 12:30:24 PM PDT 24
Peak memory 197888 kb
Host smart-3dff0c87-27a9-49cf-a55f-a39c5d35a1fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252136118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1252136118
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1103735666
Short name T724
Test name
Test status
Simulation time 59750527 ps
CPU time 0.85 seconds
Started Mar 12 12:30:32 PM PDT 24
Finished Mar 12 12:30:33 PM PDT 24
Peak memory 197880 kb
Host smart-4bd861ba-c4d8-43ea-abf5-b68ea9c7b645
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103735666 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1103735666
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2147628560
Short name T78
Test name
Test status
Simulation time 13718819 ps
CPU time 0.63 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 193580 kb
Host smart-8c3153b6-8cd4-48a3-ac10-961500c3b876
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147628560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2147628560
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.980560469
Short name T734
Test name
Test status
Simulation time 42214513 ps
CPU time 0.62 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 193772 kb
Host smart-c4478707-f945-43cd-bd5e-9c042117f376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980560469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.980560469
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1663289120
Short name T780
Test name
Test status
Simulation time 30284035 ps
CPU time 0.72 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 196160 kb
Host smart-42e97293-7d64-49e0-b0ef-3ab20d9eee66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663289120 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1663289120
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1524650515
Short name T772
Test name
Test status
Simulation time 135366221 ps
CPU time 1.64 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:13 PM PDT 24
Peak memory 198020 kb
Host smart-63c7d7cc-24f9-4e7c-a1c8-d7cf91fd6830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524650515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1524650515
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2424949006
Short name T717
Test name
Test status
Simulation time 21909304 ps
CPU time 0.75 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 197988 kb
Host smart-25575501-9561-473c-a4d4-e57009e181f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424949006 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2424949006
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1105062160
Short name T777
Test name
Test status
Simulation time 15335624 ps
CPU time 0.6 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 195208 kb
Host smart-2a6a24a8-8722-4f14-977b-3358248416d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105062160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1105062160
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3170429188
Short name T751
Test name
Test status
Simulation time 76044613 ps
CPU time 0.59 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 193620 kb
Host smart-375da97e-34ae-425f-8db5-a5afafaecf91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170429188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3170429188
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.659342448
Short name T806
Test name
Test status
Simulation time 20685497 ps
CPU time 0.69 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:23 PM PDT 24
Peak memory 194932 kb
Host smart-86167917-f404-4d63-8772-2ccc754baa4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659342448 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.659342448
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2206562771
Short name T719
Test name
Test status
Simulation time 38126528 ps
CPU time 2.01 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 198164 kb
Host smart-f516138a-9ff7-4a34-b1b8-f5b905674aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206562771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2206562771
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3723893640
Short name T816
Test name
Test status
Simulation time 79792908 ps
CPU time 0.86 seconds
Started Mar 12 12:30:21 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 197736 kb
Host smart-1df55889-3cff-42ea-98aa-e5d0ff5c55f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723893640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3723893640
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2322463397
Short name T83
Test name
Test status
Simulation time 14064250 ps
CPU time 0.74 seconds
Started Mar 12 12:30:05 PM PDT 24
Finished Mar 12 12:30:06 PM PDT 24
Peak memory 195584 kb
Host smart-55a6bf93-22e7-478c-ad67-a06aefab9ce9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322463397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2322463397
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.525019257
Short name T87
Test name
Test status
Simulation time 231927901 ps
CPU time 2.28 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 196676 kb
Host smart-c02d1d0a-dfa0-44b0-90a4-e11299d8a710
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525019257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.525019257
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.549332732
Short name T739
Test name
Test status
Simulation time 43911625 ps
CPU time 0.62 seconds
Started Mar 12 12:30:06 PM PDT 24
Finished Mar 12 12:30:06 PM PDT 24
Peak memory 195080 kb
Host smart-b1ce0748-4ba2-4642-84d9-23ad24fd3b8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549332732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.549332732
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.714994986
Short name T786
Test name
Test status
Simulation time 52227985 ps
CPU time 0.86 seconds
Started Mar 12 12:30:08 PM PDT 24
Finished Mar 12 12:30:08 PM PDT 24
Peak memory 197924 kb
Host smart-99fec8ab-3656-464f-95fb-5f4954ad3675
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714994986 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.714994986
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3519443364
Short name T798
Test name
Test status
Simulation time 12748627 ps
CPU time 0.61 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 195144 kb
Host smart-e9586b86-e179-4274-a0b3-3f621bbf4493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519443364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3519443364
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1218258095
Short name T825
Test name
Test status
Simulation time 22807398 ps
CPU time 0.57 seconds
Started Mar 12 12:30:05 PM PDT 24
Finished Mar 12 12:30:06 PM PDT 24
Peak memory 193632 kb
Host smart-e8b71f52-45ac-410f-969b-3ba98b97f989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218258095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1218258095
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1494562583
Short name T771
Test name
Test status
Simulation time 144807549 ps
CPU time 0.86 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 196160 kb
Host smart-6cd47969-46b1-40c9-bb80-fa2a7a6069c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494562583 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1494562583
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3204643685
Short name T757
Test name
Test status
Simulation time 126013206 ps
CPU time 2.39 seconds
Started Mar 12 12:30:17 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 198108 kb
Host smart-6f626a48-e598-4bf1-b36e-db6a7f11d9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204643685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3204643685
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3414832798
Short name T808
Test name
Test status
Simulation time 49514317 ps
CPU time 0.9 seconds
Started Mar 12 12:29:59 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 197148 kb
Host smart-b5d0a763-aeeb-40e3-a940-6af3576743bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414832798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3414832798
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1872267003
Short name T811
Test name
Test status
Simulation time 44605829 ps
CPU time 0.58 seconds
Started Mar 12 12:30:37 PM PDT 24
Finished Mar 12 12:30:38 PM PDT 24
Peak memory 194340 kb
Host smart-14898796-a49a-4a6e-a120-91a8aeff5dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872267003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1872267003
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.92624610
Short name T796
Test name
Test status
Simulation time 16157493 ps
CPU time 0.62 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:09 PM PDT 24
Peak memory 193688 kb
Host smart-759db469-7920-4c69-b601-a3d5d183f244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92624610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.92624610
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.496918193
Short name T841
Test name
Test status
Simulation time 15204293 ps
CPU time 0.63 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 193580 kb
Host smart-c8df4b91-5c32-4ac7-aed3-4bda04d68bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496918193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.496918193
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1111372875
Short name T785
Test name
Test status
Simulation time 13724488 ps
CPU time 0.63 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 193764 kb
Host smart-bec3633c-7690-4a84-ab77-d56ce2bc03b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111372875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1111372875
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2397545400
Short name T764
Test name
Test status
Simulation time 16288436 ps
CPU time 0.69 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 194512 kb
Host smart-8def433b-a81d-471c-a0c6-8af90b21bcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397545400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2397545400
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.187617336
Short name T803
Test name
Test status
Simulation time 38185447 ps
CPU time 0.6 seconds
Started Mar 12 12:30:35 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 193668 kb
Host smart-8cf77ee6-361c-4dab-9f5b-57894ea1458e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187617336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.187617336
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4250736593
Short name T787
Test name
Test status
Simulation time 15987288 ps
CPU time 0.6 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 193704 kb
Host smart-02da53bc-9866-4cc3-8b16-47d77bb3be49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250736593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4250736593
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.250867681
Short name T776
Test name
Test status
Simulation time 26950533 ps
CPU time 0.66 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:19 PM PDT 24
Peak memory 193756 kb
Host smart-9bc0cddd-9d42-4e3d-8789-a1244dea2448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250867681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.250867681
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.664739367
Short name T761
Test name
Test status
Simulation time 17767742 ps
CPU time 0.64 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 193692 kb
Host smart-5c165789-1d21-4335-8bef-9f5c122662f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664739367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.664739367
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.801175520
Short name T836
Test name
Test status
Simulation time 19500234 ps
CPU time 0.65 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 193764 kb
Host smart-9146d0e1-4932-41ff-98fb-c8266a82b60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801175520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.801175520
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2645494614
Short name T84
Test name
Test status
Simulation time 64732767 ps
CPU time 0.75 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 195624 kb
Host smart-d532b203-2c00-4f36-9317-252c38e4367d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645494614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2645494614
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2640228742
Short name T94
Test name
Test status
Simulation time 252959421 ps
CPU time 3.32 seconds
Started Mar 12 12:30:08 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 197848 kb
Host smart-fce611b3-5708-412d-9118-41613ce7e6a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640228742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2640228742
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1947957432
Short name T773
Test name
Test status
Simulation time 66791525 ps
CPU time 0.62 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 194892 kb
Host smart-e2aaf1a3-5f05-40f6-a2c6-6aad57896543
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947957432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1947957432
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3282647845
Short name T725
Test name
Test status
Simulation time 137021251 ps
CPU time 1.04 seconds
Started Mar 12 12:30:17 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 197920 kb
Host smart-26a6f9ac-a61f-4a74-a107-83f1de2d9bd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282647845 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3282647845
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4270720666
Short name T85
Test name
Test status
Simulation time 62682491 ps
CPU time 0.62 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:01 PM PDT 24
Peak memory 195560 kb
Host smart-fd799305-4fb8-4be5-9962-d444c4983643
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270720666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4270720666
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3755235288
Short name T832
Test name
Test status
Simulation time 39190844 ps
CPU time 0.59 seconds
Started Mar 12 12:30:04 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 193552 kb
Host smart-a1651717-0f7a-4688-b44e-64195b495162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755235288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3755235288
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2700152965
Short name T781
Test name
Test status
Simulation time 33243883 ps
CPU time 0.78 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 195984 kb
Host smart-03df0062-70f9-4ea8-af6c-7ea7ba160db2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700152965 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2700152965
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3858550415
Short name T789
Test name
Test status
Simulation time 842012219 ps
CPU time 2.35 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:13 PM PDT 24
Peak memory 198220 kb
Host smart-754be618-6625-4c46-aa40-0347c8aa8bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858550415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3858550415
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1506901161
Short name T809
Test name
Test status
Simulation time 720407063 ps
CPU time 0.87 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 197320 kb
Host smart-0a71c6b2-fc5e-4107-a78f-5d7b35673c4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506901161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1506901161
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2856904965
Short name T792
Test name
Test status
Simulation time 42357266 ps
CPU time 0.62 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 193652 kb
Host smart-288f3056-ca75-4b83-95bb-5fc6f58bf40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856904965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2856904965
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4004616046
Short name T754
Test name
Test status
Simulation time 40127814 ps
CPU time 0.59 seconds
Started Mar 12 12:30:31 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 193716 kb
Host smart-ee222d4c-d62a-4cea-bc4c-117521f3570c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004616046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4004616046
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3003018442
Short name T810
Test name
Test status
Simulation time 14729609 ps
CPU time 0.6 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 193716 kb
Host smart-11075a90-4476-4789-bd32-253524251d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003018442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3003018442
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2550319564
Short name T730
Test name
Test status
Simulation time 15153737 ps
CPU time 0.59 seconds
Started Mar 12 12:30:28 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 194320 kb
Host smart-626e1381-08a2-408a-9d72-0f8367be46fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550319564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2550319564
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.7314998
Short name T830
Test name
Test status
Simulation time 26280254 ps
CPU time 0.61 seconds
Started Mar 12 12:30:24 PM PDT 24
Finished Mar 12 12:30:25 PM PDT 24
Peak memory 193680 kb
Host smart-9d969a29-37b2-4c7a-972d-02bbbaf24ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7314998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.7314998
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.589373269
Short name T819
Test name
Test status
Simulation time 130068346 ps
CPU time 0.58 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 193636 kb
Host smart-45aea46a-313e-4cdf-81c6-a18a14448e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589373269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.589373269
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3050011779
Short name T752
Test name
Test status
Simulation time 19424957 ps
CPU time 0.57 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 193672 kb
Host smart-51d54e9c-5cf4-47aa-9f20-65fd0da6f305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050011779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3050011779
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1722058723
Short name T758
Test name
Test status
Simulation time 18533219 ps
CPU time 0.59 seconds
Started Mar 12 12:30:26 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 194400 kb
Host smart-1ae8f220-bd25-4220-bc3f-11d30c602fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722058723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1722058723
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2664244027
Short name T747
Test name
Test status
Simulation time 12168190 ps
CPU time 0.58 seconds
Started Mar 12 12:30:21 PM PDT 24
Finished Mar 12 12:30:22 PM PDT 24
Peak memory 194300 kb
Host smart-ac874aa5-107b-4f8b-a296-33ed857ceb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664244027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2664244027
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3722769592
Short name T763
Test name
Test status
Simulation time 66683178 ps
CPU time 0.59 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 194312 kb
Host smart-feaccf3a-7b74-400b-ab2e-4d134b14c92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722769592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3722769592
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.269820319
Short name T824
Test name
Test status
Simulation time 50141552 ps
CPU time 0.85 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:19 PM PDT 24
Peak memory 195956 kb
Host smart-c5f99f49-8b10-4093-827b-c48c88ac5377
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269820319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.269820319
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.15364779
Short name T745
Test name
Test status
Simulation time 634325120 ps
CPU time 1.43 seconds
Started Mar 12 12:30:16 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 196552 kb
Host smart-29d537a2-c0bf-4bb2-99e7-84a2bf39875e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15364779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.15364779
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3893130243
Short name T70
Test name
Test status
Simulation time 18108643 ps
CPU time 0.63 seconds
Started Mar 12 12:30:05 PM PDT 24
Finished Mar 12 12:30:06 PM PDT 24
Peak memory 195180 kb
Host smart-ebefb6c4-3588-4462-b2f5-91ff2d4b5ca9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893130243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3893130243
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2926829566
Short name T727
Test name
Test status
Simulation time 169807163 ps
CPU time 0.98 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:24 PM PDT 24
Peak memory 197944 kb
Host smart-f897e070-ddce-4381-bb27-8b993dd669b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926829566 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2926829566
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2186359507
Short name T795
Test name
Test status
Simulation time 23187229 ps
CPU time 0.59 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:19 PM PDT 24
Peak memory 194656 kb
Host smart-76f48233-6a96-40ad-a3b1-e1e4146c32d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186359507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2186359507
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3482501913
Short name T813
Test name
Test status
Simulation time 93053493 ps
CPU time 0.57 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 193700 kb
Host smart-f7bfdd32-1ac6-4e88-8b4d-418a31ed7197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482501913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3482501913
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4023769874
Short name T93
Test name
Test status
Simulation time 334722847 ps
CPU time 0.87 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 196948 kb
Host smart-9e22a9b2-281a-48d2-bd58-c9f5b1cf9b23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023769874 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4023769874
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2156378942
Short name T768
Test name
Test status
Simulation time 70141374 ps
CPU time 1.37 seconds
Started Mar 12 12:30:16 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 198028 kb
Host smart-ede28bd9-5b07-43dc-a817-2cddc55caa8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156378942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2156378942
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3311942922
Short name T820
Test name
Test status
Simulation time 270096274 ps
CPU time 1.15 seconds
Started Mar 12 12:30:16 PM PDT 24
Finished Mar 12 12:30:17 PM PDT 24
Peak memory 198072 kb
Host smart-3514710c-d9d1-4b4d-ae4c-e2e2873bb2f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311942922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3311942922
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3294077614
Short name T829
Test name
Test status
Simulation time 35977644 ps
CPU time 0.6 seconds
Started Mar 12 12:30:20 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 193692 kb
Host smart-4606614f-0315-4eff-b05d-7c4eabfb3bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294077614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3294077614
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2840253821
Short name T735
Test name
Test status
Simulation time 18781435 ps
CPU time 0.58 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:41 PM PDT 24
Peak memory 193696 kb
Host smart-c67f8ddb-f842-46d5-be8d-85d4d46aeecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840253821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2840253821
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.62130989
Short name T826
Test name
Test status
Simulation time 15657002 ps
CPU time 0.61 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:40 PM PDT 24
Peak memory 194456 kb
Host smart-264135cb-7091-4669-9bd3-0325a3898837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62130989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.62130989
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2869060277
Short name T838
Test name
Test status
Simulation time 15083534 ps
CPU time 0.6 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:34 PM PDT 24
Peak memory 193548 kb
Host smart-429dd43c-f497-49de-8d88-38f229823895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869060277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2869060277
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.232693539
Short name T744
Test name
Test status
Simulation time 19671026 ps
CPU time 0.63 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 193620 kb
Host smart-b84720e8-7447-45cd-b7b5-a50724edb169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232693539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.232693539
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2561223739
Short name T731
Test name
Test status
Simulation time 36193225 ps
CPU time 0.6 seconds
Started Mar 12 12:31:03 PM PDT 24
Finished Mar 12 12:31:04 PM PDT 24
Peak memory 193644 kb
Host smart-7f6e2b4a-6c1c-4d7e-83ba-1b4defb4beb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561223739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2561223739
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2306829115
Short name T769
Test name
Test status
Simulation time 22244063 ps
CPU time 0.6 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 193776 kb
Host smart-aaceea32-56e7-4289-99a7-b8b54c2b002f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306829115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2306829115
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2217916683
Short name T807
Test name
Test status
Simulation time 15977674 ps
CPU time 0.58 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:21 PM PDT 24
Peak memory 194284 kb
Host smart-4aba67b6-e3f1-4ba1-baf4-ffb17a7a6922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217916683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2217916683
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4031090816
Short name T728
Test name
Test status
Simulation time 15845591 ps
CPU time 0.62 seconds
Started Mar 12 12:30:37 PM PDT 24
Finished Mar 12 12:30:38 PM PDT 24
Peak memory 193760 kb
Host smart-88e63fd1-c631-4dcd-9dac-2146e47f6cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031090816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4031090816
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.526650377
Short name T802
Test name
Test status
Simulation time 16237503 ps
CPU time 0.59 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 194284 kb
Host smart-da6eefc7-1188-4856-9ae9-eec0c800b963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526650377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.526650377
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3343858341
Short name T726
Test name
Test status
Simulation time 36997205 ps
CPU time 0.95 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 197920 kb
Host smart-11fa1227-7f65-40ba-bbfd-9f5416d489c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343858341 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3343858341
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4016921410
Short name T750
Test name
Test status
Simulation time 51003980 ps
CPU time 0.56 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 194676 kb
Host smart-23d86c7c-01b7-4053-a2c9-c533691cb645
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016921410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4016921410
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1447710354
Short name T770
Test name
Test status
Simulation time 51406754 ps
CPU time 0.62 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 193664 kb
Host smart-10f10028-f6c2-44dc-9d4d-d45d179673ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447710354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1447710354
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.43345829
Short name T774
Test name
Test status
Simulation time 27891199 ps
CPU time 0.74 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 194976 kb
Host smart-226be51f-406a-4041-9bba-15480aa628ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43345829 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.gpio_same_csr_outstanding.43345829
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1700998725
Short name T746
Test name
Test status
Simulation time 201557503 ps
CPU time 3.42 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 197940 kb
Host smart-ff2cec76-541e-44c6-8f3f-9cd24a2978d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700998725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1700998725
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1942803430
Short name T765
Test name
Test status
Simulation time 568680352 ps
CPU time 0.88 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 197824 kb
Host smart-b5fd7123-20da-41b8-80a7-da71f3f1b260
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942803430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1942803430
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4108377407
Short name T794
Test name
Test status
Simulation time 72268990 ps
CPU time 1.01 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:02 PM PDT 24
Peak memory 197860 kb
Host smart-600f382b-6e62-4e57-9fee-de9c037f58ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108377407 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4108377407
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1414796316
Short name T839
Test name
Test status
Simulation time 44498660 ps
CPU time 0.6 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:01 PM PDT 24
Peak memory 193496 kb
Host smart-a6c6d0a9-9bac-46ec-8514-9b7cf0605452
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414796316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1414796316
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3270093289
Short name T720
Test name
Test status
Simulation time 52748490 ps
CPU time 0.59 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 193740 kb
Host smart-fcdbad8c-95ef-4fbe-9e48-1551789a4236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270093289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3270093289
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2052164919
Short name T812
Test name
Test status
Simulation time 48267775 ps
CPU time 0.87 seconds
Started Mar 12 12:30:19 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 196272 kb
Host smart-42e0a0de-56a6-4de6-9057-ddacb7358b82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052164919 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2052164919
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3472145085
Short name T740
Test name
Test status
Simulation time 2730854246 ps
CPU time 2.52 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 198112 kb
Host smart-a7438878-dcaf-4594-b300-f283fa0c36cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472145085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3472145085
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1741336982
Short name T46
Test name
Test status
Simulation time 481587750 ps
CPU time 0.87 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 197544 kb
Host smart-442d4000-d5a2-4c0e-96d9-7178409c9ba9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741336982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1741336982
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2145810605
Short name T783
Test name
Test status
Simulation time 68552843 ps
CPU time 0.69 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 197884 kb
Host smart-d53f1281-f453-4bdf-b4a4-e2a0690921ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145810605 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2145810605
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2333606431
Short name T77
Test name
Test status
Simulation time 15218716 ps
CPU time 0.66 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:18 PM PDT 24
Peak memory 194980 kb
Host smart-85e1f90a-ccec-4113-a18d-38bbd736af8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333606431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2333606431
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2587115024
Short name T748
Test name
Test status
Simulation time 39504498 ps
CPU time 0.56 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 193688 kb
Host smart-6f39e831-e34a-4f4b-a54f-59a54f8e4620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587115024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2587115024
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1382400333
Short name T790
Test name
Test status
Simulation time 16736833 ps
CPU time 0.83 seconds
Started Mar 12 12:30:18 PM PDT 24
Finished Mar 12 12:30:20 PM PDT 24
Peak memory 196376 kb
Host smart-f0b4690c-cd3a-46ad-a23d-36433edf8ff9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382400333 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1382400333
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3618505723
Short name T721
Test name
Test status
Simulation time 77551768 ps
CPU time 1.56 seconds
Started Mar 12 12:30:08 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 198080 kb
Host smart-f29110fc-e01b-4187-9f8c-064f3de4b859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618505723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3618505723
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4073903675
Short name T35
Test name
Test status
Simulation time 393925956 ps
CPU time 1.42 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 198100 kb
Host smart-d380dbba-7f76-41bc-b867-72cca06d9cc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073903675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4073903675
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.92428845
Short name T737
Test name
Test status
Simulation time 100037736 ps
CPU time 0.85 seconds
Started Mar 12 12:30:06 PM PDT 24
Finished Mar 12 12:30:07 PM PDT 24
Peak memory 197952 kb
Host smart-ff3eb427-b27f-4edd-9716-69dd663e8444
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92428845 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.92428845
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3721484760
Short name T738
Test name
Test status
Simulation time 12696651 ps
CPU time 0.59 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:10 PM PDT 24
Peak memory 194584 kb
Host smart-f070a7f0-54a9-411f-8a65-b18f74b38488
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721484760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3721484760
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2543377430
Short name T723
Test name
Test status
Simulation time 41510535 ps
CPU time 0.61 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 193672 kb
Host smart-59a5153d-50be-469c-964e-ad74bc4ed782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543377430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2543377430
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.236605547
Short name T91
Test name
Test status
Simulation time 56225725 ps
CPU time 0.73 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 196928 kb
Host smart-e51ff5a7-aa52-44a6-ba93-7aff92d3ea10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236605547 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.236605547
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2228351323
Short name T722
Test name
Test status
Simulation time 25042026 ps
CPU time 1.34 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 198088 kb
Host smart-ef62d8fb-2ad4-4d1b-8fc7-12c35fd812bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228351323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2228351323
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1295739323
Short name T47
Test name
Test status
Simulation time 214200320 ps
CPU time 1.13 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 198148 kb
Host smart-091cccbb-6433-44c0-9af5-5bb10aa32939
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295739323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1295739323
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1002088625
Short name T827
Test name
Test status
Simulation time 173578902 ps
CPU time 0.79 seconds
Started Mar 12 12:30:11 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 197896 kb
Host smart-799b1e5d-0306-439d-abd0-5133611e6691
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002088625 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1002088625
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.200417764
Short name T831
Test name
Test status
Simulation time 45837487 ps
CPU time 0.62 seconds
Started Mar 12 12:30:04 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 194892 kb
Host smart-0fafcb53-3754-4b43-9f5e-430052add675
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200417764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.200417764
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3579707626
Short name T782
Test name
Test status
Simulation time 119131124 ps
CPU time 0.59 seconds
Started Mar 12 12:30:01 PM PDT 24
Finished Mar 12 12:30:02 PM PDT 24
Peak memory 193664 kb
Host smart-a77ec8a6-ff2c-4bf4-8c6a-adccd4a68360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579707626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3579707626
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.621214639
Short name T778
Test name
Test status
Simulation time 55772419 ps
CPU time 0.61 seconds
Started Mar 12 12:30:27 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 194652 kb
Host smart-bf2a30bf-a890-4771-8969-56250fe0aaf8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621214639 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.621214639
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3700923749
Short name T736
Test name
Test status
Simulation time 41840364 ps
CPU time 2.06 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:17 PM PDT 24
Peak memory 198028 kb
Host smart-07ab23d6-d9cc-4c3e-837f-4718ffee562e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700923749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3700923749
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.824301809
Short name T95
Test name
Test status
Simulation time 288033589 ps
CPU time 1.2 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:16 PM PDT 24
Peak memory 198116 kb
Host smart-163d09d4-0e53-4a33-be4b-d4ab665e61f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824301809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.824301809
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3712124292
Short name T671
Test name
Test status
Simulation time 13290503 ps
CPU time 0.57 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 194316 kb
Host smart-1a2a2c69-28bf-47e0-a861-1c1df484e96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712124292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3712124292
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4233057696
Short name T17
Test name
Test status
Simulation time 43983549 ps
CPU time 0.85 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 195524 kb
Host smart-b8f8f4ce-6a39-47b9-aa7d-34a428446a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233057696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4233057696
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3383071938
Short name T254
Test name
Test status
Simulation time 1215413667 ps
CPU time 11.21 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:20 PM PDT 24
Peak memory 197056 kb
Host smart-f3842755-5d83-4bcf-8ad8-5605456fd24a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383071938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3383071938
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.278206597
Short name T245
Test name
Test status
Simulation time 208169153 ps
CPU time 0.9 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 196672 kb
Host smart-af296860-f6c0-4102-8a1a-6606a43f8f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278206597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.278206597
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.4104988566
Short name T268
Test name
Test status
Simulation time 58885629 ps
CPU time 0.79 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 196424 kb
Host smart-fd05a27b-368d-46bf-b13d-e20d4ebcfef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104988566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.4104988566
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.520845783
Short name T370
Test name
Test status
Simulation time 53003411 ps
CPU time 2.11 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 198232 kb
Host smart-ec279ba2-f28f-4f75-9a0c-f19092b32759
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520845783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.520845783
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.558257943
Short name T131
Test name
Test status
Simulation time 87573322 ps
CPU time 1.67 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 195872 kb
Host smart-97f0ff11-074e-4ab6-a3c7-3bea290fdcd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558257943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.558257943
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2277352863
Short name T652
Test name
Test status
Simulation time 96129789 ps
CPU time 0.95 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 196916 kb
Host smart-47f8bf5e-432d-408e-a8ae-0118f12df58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277352863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2277352863
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1449099295
Short name T412
Test name
Test status
Simulation time 226448260 ps
CPU time 1.24 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 195984 kb
Host smart-e5711fe0-760d-474c-b876-ec0b4c6e5ad8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449099295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1449099295
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2250709688
Short name T462
Test name
Test status
Simulation time 66331307 ps
CPU time 1.5 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 198140 kb
Host smart-2e1e292a-5125-40ea-a237-4c0349017ec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250709688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2250709688
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.342289772
Short name T39
Test name
Test status
Simulation time 61148520 ps
CPU time 0.87 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 213828 kb
Host smart-1e1cea72-25b9-41fc-8d68-f5e50fe7f1ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342289772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.342289772
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1606409048
Short name T264
Test name
Test status
Simulation time 92588469 ps
CPU time 1.32 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196440 kb
Host smart-4c152e6c-6a37-4bb8-9ae3-928e602645d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606409048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1606409048
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.287532580
Short name T669
Test name
Test status
Simulation time 193395945 ps
CPU time 1.41 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 196864 kb
Host smart-da9e526a-31dd-4b47-a425-d1b1d37c1c09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287532580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.287532580
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.456257923
Short name T118
Test name
Test status
Simulation time 4181140671 ps
CPU time 102.47 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 198244 kb
Host smart-51f08dc1-ec56-427a-b866-260871112a9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456257923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.456257923
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.636928169
Short name T605
Test name
Test status
Simulation time 8600190532 ps
CPU time 271.83 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:57:34 PM PDT 24
Peak memory 198432 kb
Host smart-d0bff40f-a009-426c-9def-882018c25053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=636928169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.636928169
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2117312634
Short name T540
Test name
Test status
Simulation time 28587859 ps
CPU time 0.56 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 194012 kb
Host smart-7095617e-b1cd-4647-840d-c89464465a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117312634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2117312634
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.774008716
Short name T262
Test name
Test status
Simulation time 26702547 ps
CPU time 0.85 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:52:59 PM PDT 24
Peak memory 196576 kb
Host smart-fb3026a9-0444-4b7e-b09c-0b3020c291a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774008716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.774008716
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.452764569
Short name T355
Test name
Test status
Simulation time 1466794378 ps
CPU time 21.99 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 197028 kb
Host smart-99c66bbc-ddb9-4191-adad-0fcebe9f4a63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452764569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.452764569
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2225690865
Short name T322
Test name
Test status
Simulation time 83368346 ps
CPU time 0.65 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 194576 kb
Host smart-8b0cc323-62db-463c-959a-6193efa0dc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225690865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2225690865
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3409474718
Short name T174
Test name
Test status
Simulation time 95837890 ps
CPU time 0.81 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 195708 kb
Host smart-c3d09123-af4d-46fd-b8ad-c3285324e6cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409474718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3409474718
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2380359081
Short name T561
Test name
Test status
Simulation time 53888636 ps
CPU time 2.12 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 198120 kb
Host smart-fc05af1b-d141-4806-94c4-56578b9b5fb0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380359081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2380359081
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.251706625
Short name T221
Test name
Test status
Simulation time 117850146 ps
CPU time 1.66 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:52:59 PM PDT 24
Peak memory 196588 kb
Host smart-f94a8d5c-d77d-4052-a50c-b8fdbe27889c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251706625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.251706625
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2555778112
Short name T232
Test name
Test status
Simulation time 75691764 ps
CPU time 0.99 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 196084 kb
Host smart-382b56da-1c1e-4e8d-9b29-8b478ba4009a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555778112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2555778112
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3438417202
Short name T494
Test name
Test status
Simulation time 29430681 ps
CPU time 1.03 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 196676 kb
Host smart-e3fc37a4-934d-4fb9-b51d-e3082f37d517
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438417202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3438417202
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.623359692
Short name T115
Test name
Test status
Simulation time 173652283 ps
CPU time 2.96 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:53:00 PM PDT 24
Peak memory 198044 kb
Host smart-52a03313-9d57-49a0-b38f-40dacd139a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623359692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.623359692
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2756334599
Short name T163
Test name
Test status
Simulation time 326810530 ps
CPU time 1.25 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 196884 kb
Host smart-f2a00db4-d529-4eba-9294-18b5b9debc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756334599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2756334599
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1562870862
Short name T147
Test name
Test status
Simulation time 70491094 ps
CPU time 1.08 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 195632 kb
Host smart-1f8af0ad-caf7-4b69-a894-b87c32f83001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562870862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1562870862
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3226011421
Short name T201
Test name
Test status
Simulation time 6493481785 ps
CPU time 93.79 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:54:28 PM PDT 24
Peak memory 198212 kb
Host smart-ca0153c2-a21e-4e45-87d6-3bb8dbab50bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226011421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3226011421
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4111188606
Short name T467
Test name
Test status
Simulation time 28078377 ps
CPU time 0.6 seconds
Started Mar 12 12:53:16 PM PDT 24
Finished Mar 12 12:53:17 PM PDT 24
Peak memory 194260 kb
Host smart-62c2ad26-0a52-4466-8b3e-2639b9089121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111188606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4111188606
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1063627923
Short name T246
Test name
Test status
Simulation time 43972435 ps
CPU time 0.89 seconds
Started Mar 12 12:53:13 PM PDT 24
Finished Mar 12 12:53:15 PM PDT 24
Peak memory 197360 kb
Host smart-67a91a90-0562-4366-aac0-5f114f44f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063627923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1063627923
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.482917146
Short name T165
Test name
Test status
Simulation time 1697769925 ps
CPU time 14.84 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:21 PM PDT 24
Peak memory 198152 kb
Host smart-f3574bd4-c29a-4a8c-97e5-58d8f6d7f40a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482917146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.482917146
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.130428751
Short name T405
Test name
Test status
Simulation time 16694432 ps
CPU time 0.61 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 194488 kb
Host smart-47712c4b-99cd-4166-bcbc-23c19ab97a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130428751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.130428751
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4124319466
Short name T366
Test name
Test status
Simulation time 143101633 ps
CPU time 0.86 seconds
Started Mar 12 12:53:26 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 196708 kb
Host smart-c6b2f7ef-0715-4a4f-83f1-438ab0d02cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124319466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4124319466
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2745944707
Short name T284
Test name
Test status
Simulation time 522266699 ps
CPU time 2.83 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:13 PM PDT 24
Peak memory 198156 kb
Host smart-c83dfd89-b026-45d6-bba9-3f4a8ee3f5cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745944707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2745944707
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.195898070
Short name T437
Test name
Test status
Simulation time 523079118 ps
CPU time 3.08 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 198152 kb
Host smart-f9db596e-2383-481d-a483-da1e35ec9a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195898070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
195898070
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1166908106
Short name T509
Test name
Test status
Simulation time 25129680 ps
CPU time 0.93 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 196884 kb
Host smart-34c5ab7e-f36e-4b37-b5a8-8786cdcd0547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166908106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1166908106
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1620994552
Short name T689
Test name
Test status
Simulation time 84894221 ps
CPU time 0.67 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 195300 kb
Host smart-8d61eff7-5595-4009-ad4c-938d8677424b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620994552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1620994552
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1714675754
Short name T213
Test name
Test status
Simulation time 51392992 ps
CPU time 0.94 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 198032 kb
Host smart-4d762d14-d061-41e5-af7f-dbecf2c40f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714675754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1714675754
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2928441265
Short name T237
Test name
Test status
Simulation time 231628987 ps
CPU time 1 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 195840 kb
Host smart-0b5bbc4e-011f-41d3-bee5-fef3d9b3a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928441265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2928441265
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4107736483
Short name T296
Test name
Test status
Simulation time 198854746 ps
CPU time 1.09 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196592 kb
Host smart-f57bf1c1-62d3-42bc-8e36-b1ebf120bcd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107736483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4107736483
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3664586342
Short name T691
Test name
Test status
Simulation time 1139445205 ps
CPU time 32.8 seconds
Started Mar 12 12:53:19 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 198000 kb
Host smart-94f34a3d-b6b2-4ca9-8459-43d34c35d2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664586342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3664586342
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2629256409
Short name T60
Test name
Test status
Simulation time 212900567203 ps
CPU time 858.02 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 01:07:23 PM PDT 24
Peak memory 198460 kb
Host smart-e2dc4497-8d16-4822-b8ae-097f78156013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2629256409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2629256409
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3335830265
Short name T510
Test name
Test status
Simulation time 124710258 ps
CPU time 0.56 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:26 PM PDT 24
Peak memory 195112 kb
Host smart-bdf9ee27-8c0e-40c3-bec3-a5db19187d14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335830265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3335830265
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3324747070
Short name T332
Test name
Test status
Simulation time 22677657 ps
CPU time 0.71 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:24 PM PDT 24
Peak memory 194808 kb
Host smart-d441f68e-c4dc-4db2-9ac4-5d9f01c2b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324747070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3324747070
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2825834224
Short name T354
Test name
Test status
Simulation time 1650531957 ps
CPU time 19.13 seconds
Started Mar 12 12:53:11 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 197212 kb
Host smart-e6178016-7675-4e2f-83e1-b040b8cc9dbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825834224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2825834224
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.4263691080
Short name T701
Test name
Test status
Simulation time 84636791 ps
CPU time 0.68 seconds
Started Mar 12 12:53:13 PM PDT 24
Finished Mar 12 12:53:14 PM PDT 24
Peak memory 195424 kb
Host smart-46af3563-8759-4e96-9c9b-61af11582c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263691080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.4263691080
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2010871016
Short name T150
Test name
Test status
Simulation time 30690902 ps
CPU time 0.8 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 195424 kb
Host smart-dee45754-52c7-43f5-926c-f30959ea194b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010871016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2010871016
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4189451884
Short name T375
Test name
Test status
Simulation time 126956770 ps
CPU time 2.74 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 198236 kb
Host smart-77a8f6cc-c216-45dd-911a-6e99b7688eab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189451884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4189451884
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3468209487
Short name T269
Test name
Test status
Simulation time 390091555 ps
CPU time 2.05 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 197572 kb
Host smart-9798099c-2559-4597-9dc2-5faaaf872f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468209487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3468209487
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1752022363
Short name T447
Test name
Test status
Simulation time 83296592 ps
CPU time 1.01 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 196024 kb
Host smart-fd014ea7-44ae-4e05-841a-f8d9d1fc4f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752022363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1752022363
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3384228540
Short name T583
Test name
Test status
Simulation time 29607706 ps
CPU time 0.78 seconds
Started Mar 12 12:53:18 PM PDT 24
Finished Mar 12 12:53:18 PM PDT 24
Peak memory 195432 kb
Host smart-614cff59-5a43-436d-9465-91314c9371ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384228540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3384228540
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1535116412
Short name T417
Test name
Test status
Simulation time 292717696 ps
CPU time 4.6 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 198020 kb
Host smart-8f949226-6b49-4e03-bba2-d7372f119067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535116412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1535116412
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.427058607
Short name T715
Test name
Test status
Simulation time 39894423 ps
CPU time 1.17 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 196664 kb
Host smart-effa989b-15ee-4a11-aadc-caf817d625a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427058607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.427058607
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.872506194
Short name T167
Test name
Test status
Simulation time 50917243 ps
CPU time 1.11 seconds
Started Mar 12 12:53:10 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 195720 kb
Host smart-ace1f13f-c419-43ad-8432-3959c6a9fa83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872506194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.872506194
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3002292312
Short name T500
Test name
Test status
Simulation time 2490982091 ps
CPU time 56.74 seconds
Started Mar 12 12:53:23 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 198340 kb
Host smart-6e82ac30-d1ff-4fc0-95ba-8aeb7b1f7e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002292312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3002292312
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1573210318
Short name T63
Test name
Test status
Simulation time 206570837999 ps
CPU time 1025.59 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 01:10:15 PM PDT 24
Peak memory 198432 kb
Host smart-1832fa7a-4917-4b9b-837f-45066d9e283d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1573210318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1573210318
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3537121849
Short name T446
Test name
Test status
Simulation time 15166588 ps
CPU time 0.56 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 194780 kb
Host smart-dab1379e-c80f-4582-9732-06618c92d8b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537121849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3537121849
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4050004855
Short name T466
Test name
Test status
Simulation time 75028009 ps
CPU time 0.64 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 194832 kb
Host smart-628e634d-f959-4947-8710-74d897cc8370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050004855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4050004855
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.973803478
Short name T399
Test name
Test status
Simulation time 1299804689 ps
CPU time 22.55 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:51 PM PDT 24
Peak memory 198144 kb
Host smart-474948e9-990c-48d5-9737-3f4b34647d8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973803478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.973803478
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4201634355
Short name T19
Test name
Test status
Simulation time 58827792 ps
CPU time 0.65 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:21 PM PDT 24
Peak memory 194388 kb
Host smart-ca67eeaf-d5f2-4c5f-a3fe-5a437d1e3b52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201634355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4201634355
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.4004399784
Short name T304
Test name
Test status
Simulation time 53983645 ps
CPU time 1.38 seconds
Started Mar 12 12:53:15 PM PDT 24
Finished Mar 12 12:53:17 PM PDT 24
Peak memory 197152 kb
Host smart-4a460a29-1ec0-4c77-837b-afca74429a7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004399784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.4004399784
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1946794052
Short name T362
Test name
Test status
Simulation time 44333579 ps
CPU time 1.05 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 197148 kb
Host smart-b7e2407b-d34c-4f35-b082-5c3d2b44eae5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946794052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1946794052
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.687180566
Short name T258
Test name
Test status
Simulation time 111497249 ps
CPU time 2.47 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:13 PM PDT 24
Peak memory 197316 kb
Host smart-9104b4b2-b926-4ade-a48c-b1caf52355f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687180566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
687180566
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.471837775
Short name T568
Test name
Test status
Simulation time 70389112 ps
CPU time 0.88 seconds
Started Mar 12 12:53:13 PM PDT 24
Finished Mar 12 12:53:14 PM PDT 24
Peak memory 196016 kb
Host smart-3a0f2b90-9504-4af7-b55d-b1481a9e71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471837775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.471837775
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1293795647
Short name T166
Test name
Test status
Simulation time 122802029 ps
CPU time 0.91 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 195908 kb
Host smart-1e9d529a-975c-4466-b62c-0df3068660a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293795647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1293795647
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2915577986
Short name T658
Test name
Test status
Simulation time 184215427 ps
CPU time 2.62 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 198120 kb
Host smart-fa5fb6a8-a713-499c-8eac-f6d1fbd25a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915577986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2915577986
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1263211601
Short name T660
Test name
Test status
Simulation time 37701146 ps
CPU time 1.1 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:10 PM PDT 24
Peak memory 196444 kb
Host smart-ded725ba-224f-43f1-bf2f-7a925a6421cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263211601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1263211601
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1646357844
Short name T426
Test name
Test status
Simulation time 171185224 ps
CPU time 1.27 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 196840 kb
Host smart-499e943e-13a1-4765-ac57-51cfac4923f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646357844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1646357844
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1308739001
Short name T209
Test name
Test status
Simulation time 54262378171 ps
CPU time 163.65 seconds
Started Mar 12 12:53:23 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 198324 kb
Host smart-a62788ad-93e3-494b-858f-46c1292c157b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308739001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1308739001
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1163596150
Short name T61
Test name
Test status
Simulation time 530143891025 ps
CPU time 1153.68 seconds
Started Mar 12 12:53:17 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 198424 kb
Host smart-4ecebbf6-70d5-4fa6-87aa-482343dfbbf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1163596150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1163596150
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2882571346
Short name T342
Test name
Test status
Simulation time 39980708 ps
CPU time 0.57 seconds
Started Mar 12 12:53:33 PM PDT 24
Finished Mar 12 12:53:33 PM PDT 24
Peak memory 194104 kb
Host smart-f59283dc-1a9f-4571-950a-0b6a82d9ab78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882571346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2882571346
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1563989240
Short name T632
Test name
Test status
Simulation time 22871918 ps
CPU time 0.76 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 195348 kb
Host smart-e426a427-3d06-4220-9017-33e7d8441f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563989240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1563989240
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2606251225
Short name T124
Test name
Test status
Simulation time 2248722097 ps
CPU time 16.55 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:45 PM PDT 24
Peak memory 197120 kb
Host smart-9386dc61-9033-4d12-8417-47004eef6737
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606251225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2606251225
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.647749160
Short name T175
Test name
Test status
Simulation time 178012454 ps
CPU time 0.8 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:21 PM PDT 24
Peak memory 196136 kb
Host smart-b84e2ea0-51a4-43ad-befb-7d7837021388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647749160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.647749160
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1268418904
Short name T374
Test name
Test status
Simulation time 370689874 ps
CPU time 1 seconds
Started Mar 12 12:53:26 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 195916 kb
Host smart-df76a575-84a1-4ebd-9e9e-5d832f899d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268418904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1268418904
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2637980816
Short name T161
Test name
Test status
Simulation time 557419202 ps
CPU time 1.53 seconds
Started Mar 12 12:53:19 PM PDT 24
Finished Mar 12 12:53:21 PM PDT 24
Peak memory 196712 kb
Host smart-f8bfd192-099d-4692-987a-545d5259f035
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637980816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2637980816
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1212884986
Short name T409
Test name
Test status
Simulation time 203066353 ps
CPU time 1.3 seconds
Started Mar 12 12:53:22 PM PDT 24
Finished Mar 12 12:53:23 PM PDT 24
Peak memory 195900 kb
Host smart-5d9566fc-31d1-4c71-a921-4fac52e5c8a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212884986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1212884986
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2471811838
Short name T551
Test name
Test status
Simulation time 49279685 ps
CPU time 0.99 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 12:53:42 PM PDT 24
Peak memory 195932 kb
Host smart-87111061-817e-48b1-a3e3-87685863ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471811838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2471811838
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1848466816
Short name T424
Test name
Test status
Simulation time 41975097 ps
CPU time 1.06 seconds
Started Mar 12 12:53:31 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 196056 kb
Host smart-43db17b5-d735-40bd-8eec-0fc97bd1f129
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848466816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1848466816
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2183786766
Short name T295
Test name
Test status
Simulation time 106635729 ps
CPU time 5.01 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 198128 kb
Host smart-d1333caf-e8dd-47da-ab08-c256412cea8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183786766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2183786766
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.475482232
Short name T519
Test name
Test status
Simulation time 34113048 ps
CPU time 0.81 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 196088 kb
Host smart-36890175-9753-4ba5-9ee8-5b194483c10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475482232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.475482232
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1766336293
Short name T505
Test name
Test status
Simulation time 33498972 ps
CPU time 0.85 seconds
Started Mar 12 12:53:31 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 195420 kb
Host smart-320126ad-dea1-4ffa-862c-f19e13fd6ada
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766336293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1766336293
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.489554022
Short name T357
Test name
Test status
Simulation time 20353143536 ps
CPU time 64.52 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 198304 kb
Host smart-47bc7ff7-47fe-4efb-b346-febe55c86d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489554022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.489554022
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1615438039
Short name T306
Test name
Test status
Simulation time 13836305 ps
CPU time 0.57 seconds
Started Mar 12 12:53:37 PM PDT 24
Finished Mar 12 12:53:38 PM PDT 24
Peak memory 193992 kb
Host smart-7f8ff3ec-ac76-447a-9024-dec117242b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615438039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1615438039
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2302293429
Short name T195
Test name
Test status
Simulation time 72776732 ps
CPU time 0.85 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 196540 kb
Host smart-2e40aaa5-7853-462f-92c0-ce4bc4b26840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302293429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2302293429
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2825601471
Short name T13
Test name
Test status
Simulation time 850406462 ps
CPU time 24.04 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 197020 kb
Host smart-993df46b-93c0-4f86-a5cc-e537f2b16f42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825601471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2825601471
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3282803559
Short name T363
Test name
Test status
Simulation time 739870675 ps
CPU time 0.8 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 196004 kb
Host smart-73e956ef-674f-45be-be6c-d0bfb2632733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282803559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3282803559
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2102006398
Short name T119
Test name
Test status
Simulation time 287865019 ps
CPU time 1.29 seconds
Started Mar 12 12:53:22 PM PDT 24
Finished Mar 12 12:53:23 PM PDT 24
Peak memory 197528 kb
Host smart-1c61664e-0031-4797-b674-a45993603918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102006398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2102006398
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3004139421
Short name T137
Test name
Test status
Simulation time 78030680 ps
CPU time 3.21 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 198204 kb
Host smart-1d48f1c2-be25-4a84-aa01-2544348ac5eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004139421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3004139421
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3812444278
Short name T351
Test name
Test status
Simulation time 391992709 ps
CPU time 1.75 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 195916 kb
Host smart-25370bf5-361f-49b3-8d9d-c143d859dd41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812444278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3812444278
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2128820580
Short name T151
Test name
Test status
Simulation time 180061368 ps
CPU time 1.02 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 196092 kb
Host smart-8ff96137-83cf-4072-bb8a-1e22bd2e293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128820580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2128820580
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.775856845
Short name T621
Test name
Test status
Simulation time 167736244 ps
CPU time 1.24 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 197148 kb
Host smart-de2ea036-c81d-46c6-9c3d-d7968ab0904d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775856845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.775856845
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4116030914
Short name T114
Test name
Test status
Simulation time 213039657 ps
CPU time 2.47 seconds
Started Mar 12 12:53:26 PM PDT 24
Finished Mar 12 12:53:29 PM PDT 24
Peak memory 198060 kb
Host smart-bbccf3a7-262d-4d5d-b5d6-ba25361434b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116030914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4116030914
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2623992447
Short name T408
Test name
Test status
Simulation time 55064631 ps
CPU time 0.93 seconds
Started Mar 12 12:53:26 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 195828 kb
Host smart-b2fcaaac-0806-4c43-b9b1-49f3b09b7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623992447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2623992447
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2118777341
Short name T273
Test name
Test status
Simulation time 171557164 ps
CPU time 0.94 seconds
Started Mar 12 12:53:19 PM PDT 24
Finished Mar 12 12:53:20 PM PDT 24
Peak memory 195468 kb
Host smart-f52a2f7a-58dd-4900-b37e-9cc7c2a724b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118777341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2118777341
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2308443356
Short name T301
Test name
Test status
Simulation time 10990412134 ps
CPU time 43.98 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 198188 kb
Host smart-d23ea0b2-bd65-4980-ae21-8ae0fb56df2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308443356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2308443356
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1921077637
Short name T549
Test name
Test status
Simulation time 62010906 ps
CPU time 0.58 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 194052 kb
Host smart-2761b507-1700-4664-9355-bc0af2c95589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921077637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1921077637
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2788290833
Short name T193
Test name
Test status
Simulation time 31099575 ps
CPU time 0.85 seconds
Started Mar 12 12:53:31 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 196320 kb
Host smart-71cd0cee-1b2c-41fe-8122-0a55696c207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788290833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2788290833
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2684710019
Short name T646
Test name
Test status
Simulation time 589570319 ps
CPU time 19.86 seconds
Started Mar 12 12:53:34 PM PDT 24
Finished Mar 12 12:53:53 PM PDT 24
Peak memory 198152 kb
Host smart-710d2dab-be8a-47f1-a35f-48c76c4896f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684710019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2684710019
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1766177985
Short name T559
Test name
Test status
Simulation time 45484292 ps
CPU time 0.75 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 196708 kb
Host smart-237e05c7-a1a8-4838-a42d-c30cb0f3216a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766177985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1766177985
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.296673427
Short name T391
Test name
Test status
Simulation time 79406412 ps
CPU time 1.31 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:26 PM PDT 24
Peak memory 197156 kb
Host smart-907c67c0-5422-467b-a719-bc091712e29c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296673427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.296673427
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2078453332
Short name T205
Test name
Test status
Simulation time 24546805 ps
CPU time 1.06 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:29 PM PDT 24
Peak memory 196340 kb
Host smart-94efabef-1475-4ffd-8913-293e242b5f7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078453332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2078453332
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1977726538
Short name T294
Test name
Test status
Simulation time 34385131 ps
CPU time 1 seconds
Started Mar 12 12:53:34 PM PDT 24
Finished Mar 12 12:53:35 PM PDT 24
Peak memory 195680 kb
Host smart-f2bd9d6c-0806-4ee1-ac9d-6537fa711e44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977726538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1977726538
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3896098187
Short name T609
Test name
Test status
Simulation time 65488119 ps
CPU time 1.21 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 195968 kb
Host smart-62324852-88f7-4aff-9d39-9a6452498d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896098187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3896098187
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3266760773
Short name T344
Test name
Test status
Simulation time 403803260 ps
CPU time 1.29 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 195968 kb
Host smart-fdc6e431-ca14-427a-8690-9eac9fc329a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266760773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3266760773
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.704026281
Short name T128
Test name
Test status
Simulation time 1284054406 ps
CPU time 4.61 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:35 PM PDT 24
Peak memory 198184 kb
Host smart-14a3b373-68f6-4c9d-abab-0ac3833a69ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704026281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.704026281
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1839986632
Short name T130
Test name
Test status
Simulation time 173851110 ps
CPU time 1.27 seconds
Started Mar 12 12:53:32 PM PDT 24
Finished Mar 12 12:53:33 PM PDT 24
Peak memory 195776 kb
Host smart-996e3480-17e1-4b83-8b52-c78aac7ed5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839986632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1839986632
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1893954939
Short name T283
Test name
Test status
Simulation time 57505531 ps
CPU time 1.2 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 195964 kb
Host smart-ad4dba9e-c2c2-4245-a035-01ce173271fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893954939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1893954939
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.515720957
Short name T152
Test name
Test status
Simulation time 6306470993 ps
CPU time 61.02 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 198300 kb
Host smart-faf695b8-37f9-4e3a-9b0b-78fa433706a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515720957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.515720957
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4284469428
Short name T335
Test name
Test status
Simulation time 260792400 ps
CPU time 0.72 seconds
Started Mar 12 12:53:33 PM PDT 24
Finished Mar 12 12:53:34 PM PDT 24
Peak memory 195164 kb
Host smart-96742d1b-5b3a-4191-baf6-1e7ed4106cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284469428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4284469428
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1557595905
Short name T382
Test name
Test status
Simulation time 951465142 ps
CPU time 13.1 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:43 PM PDT 24
Peak memory 195684 kb
Host smart-778c8ffd-e65d-4a34-86d4-da30591f8c3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557595905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1557595905
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1030471200
Short name T105
Test name
Test status
Simulation time 49833051 ps
CPU time 0.78 seconds
Started Mar 12 12:53:39 PM PDT 24
Finished Mar 12 12:53:40 PM PDT 24
Peak memory 195864 kb
Host smart-39459eed-4e6c-4550-9b19-d927744c7ed3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030471200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1030471200
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2650224822
Short name T120
Test name
Test status
Simulation time 103789629 ps
CPU time 0.76 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 195436 kb
Host smart-8ef70488-6503-4cf2-b014-fda4f1113380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650224822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2650224822
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2102469124
Short name T512
Test name
Test status
Simulation time 82908161 ps
CPU time 3.09 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:23 PM PDT 24
Peak memory 196404 kb
Host smart-1309c8e4-bd04-41f3-866b-1d65dc2f09e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102469124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2102469124
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3853403198
Short name T123
Test name
Test status
Simulation time 159047280 ps
CPU time 3.28 seconds
Started Mar 12 12:53:40 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 198180 kb
Host smart-8c1cf6e7-c5c5-499c-a14a-082c0ef0d00b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853403198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3853403198
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.893316878
Short name T110
Test name
Test status
Simulation time 52864985 ps
CPU time 0.7 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 196160 kb
Host smart-69b8166c-be07-4888-8ff8-52e8722c0e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893316878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.893316878
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3288041679
Short name T142
Test name
Test status
Simulation time 143366250 ps
CPU time 0.96 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 196188 kb
Host smart-862db582-3038-4bf8-b554-e78e73ac6330
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288041679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3288041679
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.61775533
Short name T607
Test name
Test status
Simulation time 191786612 ps
CPU time 2.2 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 198132 kb
Host smart-284ff0b5-09ec-4b71-aa0c-91f6f6f2d06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61775533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand
om_long_reg_writes_reg_reads.61775533
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2835818298
Short name T222
Test name
Test status
Simulation time 41534269 ps
CPU time 1.07 seconds
Started Mar 12 12:53:36 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 195768 kb
Host smart-41c1b86d-0c6c-4a64-a234-ad93b9ab0251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835818298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2835818298
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.637367880
Short name T662
Test name
Test status
Simulation time 37599802 ps
CPU time 1.25 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 12:53:43 PM PDT 24
Peak memory 196600 kb
Host smart-2fee2f5a-1be4-4979-9669-c5215c02bde4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637367880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.637367880
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1541263703
Short name T629
Test name
Test status
Simulation time 30416197959 ps
CPU time 175.95 seconds
Started Mar 12 12:53:39 PM PDT 24
Finished Mar 12 12:56:35 PM PDT 24
Peak memory 198112 kb
Host smart-ce2a87bf-599f-4694-a547-b0cc223467a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541263703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1541263703
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.264649684
Short name T64
Test name
Test status
Simulation time 81667792853 ps
CPU time 1138.95 seconds
Started Mar 12 12:53:34 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 198508 kb
Host smart-4839366a-41bf-4623-9639-288c5c0e4813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=264649684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.264649684
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2260496377
Short name T565
Test name
Test status
Simulation time 40334561 ps
CPU time 0.59 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 12:53:42 PM PDT 24
Peak memory 194804 kb
Host smart-24b12881-ed6f-45e4-b73c-71d85bbdd260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260496377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2260496377
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.621408272
Short name T359
Test name
Test status
Simulation time 46685535 ps
CPU time 0.64 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 194064 kb
Host smart-02d21b64-c7c7-40af-a89c-7c4328d385db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621408272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.621408272
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3774557147
Short name T458
Test name
Test status
Simulation time 268148235 ps
CPU time 13.66 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 196856 kb
Host smart-e23e01a8-4710-4c4f-b458-0759bb52fd49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774557147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3774557147
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1974074515
Short name T107
Test name
Test status
Simulation time 288057780 ps
CPU time 1.03 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:26 PM PDT 24
Peak memory 196772 kb
Host smart-6243ec5c-b0ae-4189-a578-4ff57c4ed02a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974074515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1974074515
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3109133364
Short name T625
Test name
Test status
Simulation time 213530962 ps
CPU time 1.04 seconds
Started Mar 12 12:53:27 PM PDT 24
Finished Mar 12 12:53:28 PM PDT 24
Peak memory 196944 kb
Host smart-e24c70c2-3bfc-4b3d-9ecf-371fe74a72b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109133364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3109133364
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2647814920
Short name T704
Test name
Test status
Simulation time 89354376 ps
CPU time 1.11 seconds
Started Mar 12 12:53:39 PM PDT 24
Finished Mar 12 12:53:40 PM PDT 24
Peak memory 196592 kb
Host smart-7df8b6cb-0b6e-4dc4-99c9-09d20ea4f7fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647814920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2647814920
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2565058047
Short name T636
Test name
Test status
Simulation time 144957543 ps
CPU time 2.93 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 195960 kb
Host smart-97cf0d47-08c8-46c5-b9c5-4a1697dac08b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565058047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2565058047
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3331736915
Short name T261
Test name
Test status
Simulation time 119858553 ps
CPU time 1.11 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 196088 kb
Host smart-ceaece47-7a0d-41a2-86ff-806a76f5587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331736915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3331736915
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2400941859
Short name T290
Test name
Test status
Simulation time 170320132 ps
CPU time 1.03 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:26 PM PDT 24
Peak memory 196104 kb
Host smart-4b925143-0342-4f78-a7a6-ab237f64b8ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400941859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2400941859
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3443217050
Short name T218
Test name
Test status
Simulation time 116744968 ps
CPU time 3.25 seconds
Started Mar 12 12:53:32 PM PDT 24
Finished Mar 12 12:53:35 PM PDT 24
Peak memory 198028 kb
Host smart-02db3c3c-9eb7-4658-a3d6-e04d5a80bb5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443217050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3443217050
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2124201655
Short name T594
Test name
Test status
Simulation time 207616172 ps
CPU time 1.25 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 196476 kb
Host smart-e7063860-6028-423e-a86f-02ba5c911c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124201655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2124201655
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.276600576
Short name T497
Test name
Test status
Simulation time 1054640242 ps
CPU time 1.19 seconds
Started Mar 12 12:53:38 PM PDT 24
Finished Mar 12 12:53:40 PM PDT 24
Peak memory 198044 kb
Host smart-1f99f055-ae69-45db-ab6d-5980a67285f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276600576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.276600576
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1348252021
Short name T396
Test name
Test status
Simulation time 18606820651 ps
CPU time 117.89 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:55:28 PM PDT 24
Peak memory 198324 kb
Host smart-54de5e64-0a25-4d84-9d25-879fda829686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348252021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1348252021
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.975649128
Short name T349
Test name
Test status
Simulation time 37960198 ps
CPU time 0.56 seconds
Started Mar 12 12:53:38 PM PDT 24
Finished Mar 12 12:53:39 PM PDT 24
Peak memory 194984 kb
Host smart-aa6a44ab-f48d-435a-bec9-c46bb6d17bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975649128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.975649128
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.240087932
Short name T615
Test name
Test status
Simulation time 70246981 ps
CPU time 0.85 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:29 PM PDT 24
Peak memory 197360 kb
Host smart-207a1b1a-967d-470f-9cd8-74588570a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240087932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.240087932
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3171934142
Short name T403
Test name
Test status
Simulation time 1128624643 ps
CPU time 12.78 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 198148 kb
Host smart-eac8a32c-251f-493c-9489-878e5f7a891f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171934142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3171934142
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.393683834
Short name T3
Test name
Test status
Simulation time 37598834 ps
CPU time 0.76 seconds
Started Mar 12 12:53:36 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 195424 kb
Host smart-10ffef84-afca-4b75-a415-75c8aade34c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393683834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.393683834
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.318476544
Short name T528
Test name
Test status
Simulation time 46637117 ps
CPU time 1.22 seconds
Started Mar 12 12:53:26 PM PDT 24
Finished Mar 12 12:53:27 PM PDT 24
Peak memory 197040 kb
Host smart-40db6f3c-8dda-44f9-bac1-2ddd04348973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318476544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.318476544
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3422247386
Short name T380
Test name
Test status
Simulation time 166300496 ps
CPU time 3.35 seconds
Started Mar 12 12:53:34 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 196584 kb
Host smart-b1939ca8-8606-467b-ac93-0f6abf256e74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422247386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3422247386
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2774982978
Short name T112
Test name
Test status
Simulation time 71555038 ps
CPU time 2.21 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 198196 kb
Host smart-b17ee3c2-9f7e-4e64-8094-2b175307f9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774982978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2774982978
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3444282337
Short name T584
Test name
Test status
Simulation time 27534433 ps
CPU time 1 seconds
Started Mar 12 12:53:37 PM PDT 24
Finished Mar 12 12:53:39 PM PDT 24
Peak memory 196020 kb
Host smart-0e462a26-15ed-4764-a254-80a5d3897a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444282337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3444282337
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.75054224
Short name T57
Test name
Test status
Simulation time 203507644 ps
CPU time 0.97 seconds
Started Mar 12 12:53:24 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 196540 kb
Host smart-ab844ab7-7306-4d67-b540-a3ab637e6191
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75054224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup_
pulldown.75054224
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_smoke.2713361559
Short name T427
Test name
Test status
Simulation time 319937381 ps
CPU time 1.13 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 196656 kb
Host smart-f70a8e67-a4ba-4e5d-9536-35aecf089a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713361559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2713361559
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.345260891
Short name T496
Test name
Test status
Simulation time 142865816 ps
CPU time 1.07 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:35 PM PDT 24
Peak memory 195880 kb
Host smart-9aafe4db-f955-40b1-a608-cbef9bddaae4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345260891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.345260891
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.4140885268
Short name T459
Test name
Test status
Simulation time 5013176704 ps
CPU time 130.6 seconds
Started Mar 12 12:53:40 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 198288 kb
Host smart-3f7d6d41-0fb1-4989-9c66-06281fdb914f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140885268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.4140885268
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3094259669
Short name T435
Test name
Test status
Simulation time 15197553 ps
CPU time 0.58 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 194116 kb
Host smart-e5f704c1-a6c5-45fd-843b-8dc4642cfc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094259669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3094259669
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3607014109
Short name T173
Test name
Test status
Simulation time 69406244 ps
CPU time 0.64 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:51 PM PDT 24
Peak memory 193924 kb
Host smart-3c22e490-bbd4-4838-b6d1-c96037278c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607014109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3607014109
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3787336126
Short name T569
Test name
Test status
Simulation time 347056270 ps
CPU time 18.14 seconds
Started Mar 12 12:53:40 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 196564 kb
Host smart-2848651a-770c-451d-b560-dd1e15e127c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787336126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3787336126
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1625733163
Short name T452
Test name
Test status
Simulation time 338042861 ps
CPU time 1.05 seconds
Started Mar 12 12:53:35 PM PDT 24
Finished Mar 12 12:53:36 PM PDT 24
Peak memory 197888 kb
Host smart-73b12542-6f86-4987-b9a1-556d7b569338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625733163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1625733163
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.506927601
Short name T587
Test name
Test status
Simulation time 473268891 ps
CPU time 1.46 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 197276 kb
Host smart-b798b373-4500-4df1-afb0-4f8ca79b04e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506927601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.506927601
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4216821396
Short name T178
Test name
Test status
Simulation time 71144122 ps
CPU time 1.36 seconds
Started Mar 12 12:53:36 PM PDT 24
Finished Mar 12 12:53:37 PM PDT 24
Peak memory 196736 kb
Host smart-e5d433d7-254d-48fb-a44f-afe3fbe9ac27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216821396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4216821396
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1673173447
Short name T230
Test name
Test status
Simulation time 876201226 ps
CPU time 1.76 seconds
Started Mar 12 12:53:40 PM PDT 24
Finished Mar 12 12:53:41 PM PDT 24
Peak memory 196212 kb
Host smart-4ef8f14b-7514-42a4-9d04-0954aac06925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673173447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1673173447
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.270735249
Short name T698
Test name
Test status
Simulation time 14991797 ps
CPU time 0.64 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 194432 kb
Host smart-e998f845-27c1-49ed-b103-9d2d4dd74bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270735249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.270735249
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1312362655
Short name T97
Test name
Test status
Simulation time 110856371 ps
CPU time 0.79 seconds
Started Mar 12 12:53:33 PM PDT 24
Finished Mar 12 12:53:34 PM PDT 24
Peak memory 195564 kb
Host smart-3f0096f2-9f3b-448e-a46c-cadd52528a13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312362655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1312362655
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2242509263
Short name T663
Test name
Test status
Simulation time 155173759 ps
CPU time 3.57 seconds
Started Mar 12 12:53:42 PM PDT 24
Finished Mar 12 12:53:45 PM PDT 24
Peak memory 198076 kb
Host smart-5b97dc7d-b0cb-439f-8047-bf278689e762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242509263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2242509263
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.361446125
Short name T630
Test name
Test status
Simulation time 165226034 ps
CPU time 1.22 seconds
Started Mar 12 12:53:42 PM PDT 24
Finished Mar 12 12:53:43 PM PDT 24
Peak memory 198092 kb
Host smart-4b155f7d-41fe-45d3-822b-14c74d2215a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361446125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.361446125
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1494116289
Short name T365
Test name
Test status
Simulation time 179753412 ps
CPU time 0.82 seconds
Started Mar 12 12:53:32 PM PDT 24
Finished Mar 12 12:53:33 PM PDT 24
Peak memory 195252 kb
Host smart-164e19bc-4869-4861-89bd-c0ebe4a11f80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494116289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1494116289
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.578263403
Short name T260
Test name
Test status
Simulation time 14174318126 ps
CPU time 200.81 seconds
Started Mar 12 12:53:38 PM PDT 24
Finished Mar 12 12:56:59 PM PDT 24
Peak memory 198320 kb
Host smart-1a51cfcd-10fe-41fc-9833-519b74bb8e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578263403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.578263403
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.4145791073
Short name T711
Test name
Test status
Simulation time 37083160529 ps
CPU time 380.16 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 01:00:04 PM PDT 24
Peak memory 198492 kb
Host smart-3ec703aa-393a-49b9-8510-3b3fdc287c95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4145791073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.4145791073
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3689846200
Short name T469
Test name
Test status
Simulation time 16368584 ps
CPU time 0.57 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:00 PM PDT 24
Peak memory 195004 kb
Host smart-616e23b1-c10b-4055-b5e3-47bd182c49dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689846200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3689846200
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.466467281
Short name T488
Test name
Test status
Simulation time 45949951 ps
CPU time 0.85 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 196536 kb
Host smart-8886054b-17fd-4abd-a034-0563c5b2cb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466467281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.466467281
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1037332135
Short name T100
Test name
Test status
Simulation time 7737003446 ps
CPU time 23.07 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:24 PM PDT 24
Peak memory 196764 kb
Host smart-b7aa22bf-8ec2-4c55-b0ad-54ce0bea9775
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037332135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1037332135
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3247998674
Short name T340
Test name
Test status
Simulation time 41470637 ps
CPU time 0.77 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:00 PM PDT 24
Peak memory 196024 kb
Host smart-9d96e354-7081-4180-b248-862d13825beb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247998674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3247998674
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.4233680568
Short name T618
Test name
Test status
Simulation time 86700581 ps
CPU time 0.69 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 194440 kb
Host smart-77e8a16f-e76b-47ad-abac-677671bf192e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233680568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.4233680568
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2635870953
Short name T208
Test name
Test status
Simulation time 90240553 ps
CPU time 3.23 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 198268 kb
Host smart-4f184499-d77b-4a71-99f8-8166ee919c56
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635870953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2635870953
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1726725675
Short name T16
Test name
Test status
Simulation time 134651121 ps
CPU time 2.09 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 198188 kb
Host smart-678389da-c7e2-4a1d-b02c-dff8537d3dbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726725675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1726725675
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1321339453
Short name T696
Test name
Test status
Simulation time 136907892 ps
CPU time 0.88 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 195960 kb
Host smart-17592aec-7757-4f2f-bd48-73c183efc261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321339453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1321339453
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1173971980
Short name T550
Test name
Test status
Simulation time 44625617 ps
CPU time 0.71 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 196260 kb
Host smart-e610fb9d-83b6-48a4-ad92-6b9fa0e889fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173971980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1173971980
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2633822698
Short name T302
Test name
Test status
Simulation time 422255628 ps
CPU time 5.46 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:57 PM PDT 24
Peak memory 198060 kb
Host smart-823dfa8a-9ed5-4f7c-b477-3475c16de847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633822698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2633822698
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1897303620
Short name T50
Test name
Test status
Simulation time 1171987095 ps
CPU time 0.95 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 215020 kb
Host smart-89690e7b-a18e-43f9-85a2-519bf88d1e3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897303620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1897303620
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1567545528
Short name T14
Test name
Test status
Simulation time 25775396 ps
CPU time 0.78 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 195372 kb
Host smart-1c3a23ce-d8b3-4604-8d6c-d849fd47213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567545528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1567545528
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4173701174
Short name T702
Test name
Test status
Simulation time 43077408 ps
CPU time 1.28 seconds
Started Mar 12 12:52:57 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 196888 kb
Host smart-655a85a5-18e5-46bc-82e9-40b69f21ad3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173701174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4173701174
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1098368154
Short name T538
Test name
Test status
Simulation time 15880190736 ps
CPU time 31.72 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:36 PM PDT 24
Peak memory 198184 kb
Host smart-d9df8360-3cb6-4c35-8c35-5c5b5d057ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098368154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1098368154
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3653315802
Short name T41
Test name
Test status
Simulation time 23297395 ps
CPU time 0.57 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:29 PM PDT 24
Peak memory 194032 kb
Host smart-68613300-f60b-42df-8348-7ce2527d6761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653315802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3653315802
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3360760653
Short name T649
Test name
Test status
Simulation time 32904240 ps
CPU time 0.64 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 194056 kb
Host smart-c5ae78f4-3655-43eb-b6e5-f45fdf58eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360760653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3360760653
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2861566251
Short name T599
Test name
Test status
Simulation time 403107208 ps
CPU time 5.3 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:53:48 PM PDT 24
Peak memory 198152 kb
Host smart-99a1f89d-cb20-489f-94c7-6c7b43c7a653
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861566251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2861566251
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2776306118
Short name T136
Test name
Test status
Simulation time 51249589 ps
CPU time 0.85 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 196080 kb
Host smart-1a971239-b969-4bff-8a1f-a5c7d57ee3c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776306118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2776306118
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.209279678
Short name T341
Test name
Test status
Simulation time 37094850 ps
CPU time 0.99 seconds
Started Mar 12 12:53:30 PM PDT 24
Finished Mar 12 12:53:31 PM PDT 24
Peak memory 196052 kb
Host smart-7ea37447-6733-4eb7-84b7-7ddba98de22c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209279678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.209279678
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1190972659
Short name T484
Test name
Test status
Simulation time 91620022 ps
CPU time 1.12 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 197120 kb
Host smart-8de63b3b-3b37-4ca7-9ef3-f40269f0c4e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190972659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1190972659
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3973164979
Short name T149
Test name
Test status
Simulation time 94110303 ps
CPU time 2.37 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:53:45 PM PDT 24
Peak memory 197300 kb
Host smart-6fdf015b-3c62-41d4-b233-43b146bf151d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973164979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3973164979
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2080051381
Short name T425
Test name
Test status
Simulation time 541638730 ps
CPU time 0.85 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 195416 kb
Host smart-83475445-1d0b-4889-9fe7-e21778d0c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080051381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2080051381
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2358691985
Short name T520
Test name
Test status
Simulation time 109000966 ps
CPU time 1.34 seconds
Started Mar 12 12:53:45 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 197128 kb
Host smart-175a2716-e4f4-4f08-a796-0047033f760b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358691985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2358691985
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.636840787
Short name T610
Test name
Test status
Simulation time 444961219 ps
CPU time 6.2 seconds
Started Mar 12 12:53:42 PM PDT 24
Finished Mar 12 12:53:48 PM PDT 24
Peak memory 198096 kb
Host smart-0d20ff2a-4a33-45b5-ae8c-722e365d4483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636840787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.636840787
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1716869455
Short name T557
Test name
Test status
Simulation time 197870839 ps
CPU time 1.11 seconds
Started Mar 12 12:53:31 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 196412 kb
Host smart-b3ff8ade-f344-46e2-8964-4a0d15008738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716869455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1716869455
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2202191009
Short name T29
Test name
Test status
Simulation time 36855939 ps
CPU time 1.12 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 12:53:43 PM PDT 24
Peak memory 195908 kb
Host smart-794647b3-bdb1-4990-a349-be9530e86390
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202191009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2202191009
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2706783983
Short name T263
Test name
Test status
Simulation time 22602499342 ps
CPU time 151.39 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:56:15 PM PDT 24
Peak memory 198276 kb
Host smart-3737b814-760d-465f-b882-abc0d2a0a36d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706783983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2706783983
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1239648789
Short name T239
Test name
Test status
Simulation time 17337488 ps
CPU time 0.61 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 12:53:45 PM PDT 24
Peak memory 194312 kb
Host smart-a8c91e1f-e7c3-4f68-8912-5083afd12b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239648789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1239648789
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3669599799
Short name T121
Test name
Test status
Simulation time 30644763 ps
CPU time 0.95 seconds
Started Mar 12 12:53:31 PM PDT 24
Finished Mar 12 12:53:32 PM PDT 24
Peak memory 197396 kb
Host smart-3ea994d5-f2b1-42cd-8cf7-e5bbcf49fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669599799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3669599799
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2568016306
Short name T436
Test name
Test status
Simulation time 5136113679 ps
CPU time 19.09 seconds
Started Mar 12 12:53:37 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 198240 kb
Host smart-586160af-13bf-4376-8861-ea63f3f0f750
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568016306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2568016306
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1045501054
Short name T214
Test name
Test status
Simulation time 112070955 ps
CPU time 0.71 seconds
Started Mar 12 12:53:33 PM PDT 24
Finished Mar 12 12:53:34 PM PDT 24
Peak memory 195496 kb
Host smart-584d0acd-bdc0-475e-aa44-aa8b06c84600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045501054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1045501054
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3472072490
Short name T661
Test name
Test status
Simulation time 40925102 ps
CPU time 1.14 seconds
Started Mar 12 12:53:29 PM PDT 24
Finished Mar 12 12:53:30 PM PDT 24
Peak memory 196308 kb
Host smart-c316db84-e4e3-43cf-81ea-652a0a8fc3c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472072490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3472072490
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2036436923
Short name T478
Test name
Test status
Simulation time 525181962 ps
CPU time 3.39 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 198192 kb
Host smart-89c31722-cf8c-4424-81c1-dbc1b52ee21b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036436923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2036436923
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1139137032
Short name T498
Test name
Test status
Simulation time 136754739 ps
CPU time 1.37 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:53 PM PDT 24
Peak memory 196372 kb
Host smart-98d1aedd-c88c-40ec-868c-4c58c0cbabd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139137032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1139137032
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1561006568
Short name T275
Test name
Test status
Simulation time 18254438 ps
CPU time 0.65 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 195004 kb
Host smart-dc1c2047-5daf-4c77-a2bf-4fc3bb07aa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561006568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1561006568
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3776182941
Short name T589
Test name
Test status
Simulation time 14785360 ps
CPU time 0.71 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 12:53:42 PM PDT 24
Peak memory 196184 kb
Host smart-43956e24-f787-4e64-8f3a-68af80050f7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776182941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3776182941
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.550215676
Short name T619
Test name
Test status
Simulation time 230093394 ps
CPU time 4.88 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 198044 kb
Host smart-776c8657-0a6f-40aa-b188-7e256f9f37c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550215676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.550215676
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3993769219
Short name T240
Test name
Test status
Simulation time 99017243 ps
CPU time 0.93 seconds
Started Mar 12 12:53:47 PM PDT 24
Finished Mar 12 12:53:48 PM PDT 24
Peak memory 195812 kb
Host smart-beb1c5c4-aa90-4d8f-8daa-c3666a4956d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993769219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3993769219
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1860274880
Short name T281
Test name
Test status
Simulation time 38317172 ps
CPU time 1.05 seconds
Started Mar 12 12:53:32 PM PDT 24
Finished Mar 12 12:53:33 PM PDT 24
Peak memory 195884 kb
Host smart-589fe6d6-3824-4e77-8592-9f19141e30e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860274880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1860274880
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2793116017
Short name T444
Test name
Test status
Simulation time 84603175810 ps
CPU time 60.05 seconds
Started Mar 12 12:53:53 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 198356 kb
Host smart-177ce305-08f9-499d-b675-03637d77f3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793116017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2793116017
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3866829999
Short name T62
Test name
Test status
Simulation time 51219410543 ps
CPU time 859.01 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 01:08:05 PM PDT 24
Peak memory 198476 kb
Host smart-1790d790-f814-407b-b1e4-796890e3392d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3866829999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3866829999
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4198343274
Short name T472
Test name
Test status
Simulation time 52471799 ps
CPU time 0.59 seconds
Started Mar 12 12:53:45 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 194344 kb
Host smart-323d84f6-2b17-44a4-9cf2-0b24305d6523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198343274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4198343274
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3820596579
Short name T265
Test name
Test status
Simulation time 89705591 ps
CPU time 0.92 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 197208 kb
Host smart-5a612a55-f92e-4fb0-91fc-3e61ca65a432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820596579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3820596579
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3277293581
Short name T392
Test name
Test status
Simulation time 835417832 ps
CPU time 12.95 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 197936 kb
Host smart-4a5633c8-a6d0-4abc-96e8-d955f21edf47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277293581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3277293581
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2507354132
Short name T7
Test name
Test status
Simulation time 108254752 ps
CPU time 1.15 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196780 kb
Host smart-42a5d4b9-f1c3-409a-b019-846f893cf839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507354132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2507354132
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1136786069
Short name T179
Test name
Test status
Simulation time 245982076 ps
CPU time 1.06 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 196208 kb
Host smart-f0116a5b-74de-4ab9-a92e-acc223dcb9de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136786069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1136786069
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3893084070
Short name T266
Test name
Test status
Simulation time 91470745 ps
CPU time 3.36 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:50 PM PDT 24
Peak memory 198180 kb
Host smart-bb11b45f-3930-4d75-abbd-8c59b195f6d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893084070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3893084070
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3118292983
Short name T343
Test name
Test status
Simulation time 744206358 ps
CPU time 1.96 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 196660 kb
Host smart-fea29fb2-efd7-49b9-a38a-f884a7da71ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118292983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3118292983
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1411157540
Short name T288
Test name
Test status
Simulation time 456501473 ps
CPU time 1.07 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196180 kb
Host smart-3e616f4f-31e1-4fda-b323-c2af05fd724a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411157540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1411157540
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.693379403
Short name T162
Test name
Test status
Simulation time 68052042 ps
CPU time 0.88 seconds
Started Mar 12 12:53:53 PM PDT 24
Finished Mar 12 12:53:54 PM PDT 24
Peak memory 197312 kb
Host smart-c2355d10-abfc-4572-b29a-dd677fb3c788
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693379403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.693379403
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3782550030
Short name T1
Test name
Test status
Simulation time 6545790530 ps
CPU time 5.46 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 198260 kb
Host smart-3e1264ea-f8f1-4a33-a71b-faab9c4be588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782550030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3782550030
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2687467874
Short name T220
Test name
Test status
Simulation time 278867428 ps
CPU time 1.18 seconds
Started Mar 12 12:53:47 PM PDT 24
Finished Mar 12 12:53:48 PM PDT 24
Peak memory 195916 kb
Host smart-c4276583-4919-4363-b66f-a8fa152e13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687467874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2687467874
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1237857715
Short name T577
Test name
Test status
Simulation time 29655573 ps
CPU time 0.88 seconds
Started Mar 12 12:53:52 PM PDT 24
Finished Mar 12 12:53:53 PM PDT 24
Peak memory 195568 kb
Host smart-3ec605bd-6192-453c-84b9-a27a8e9756c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237857715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1237857715
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4020465037
Short name T407
Test name
Test status
Simulation time 17157659852 ps
CPU time 212.33 seconds
Started Mar 12 12:53:49 PM PDT 24
Finished Mar 12 12:57:21 PM PDT 24
Peak memory 198244 kb
Host smart-6ccf561f-9325-4168-b3e2-17b8518c758b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020465037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4020465037
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3298900205
Short name T579
Test name
Test status
Simulation time 221238887459 ps
CPU time 1137.84 seconds
Started Mar 12 12:53:48 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 198380 kb
Host smart-f1582a75-7565-4d5a-8fd5-6bfb261ed1c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3298900205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3298900205
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3647137227
Short name T456
Test name
Test status
Simulation time 11761206 ps
CPU time 0.56 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 194056 kb
Host smart-35612f99-b012-4578-a71e-e8406ab489fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647137227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3647137227
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.343686274
Short name T291
Test name
Test status
Simulation time 163657788 ps
CPU time 0.93 seconds
Started Mar 12 12:53:48 PM PDT 24
Finished Mar 12 12:53:49 PM PDT 24
Peak memory 197256 kb
Host smart-4661e211-5acc-4eb3-bb83-f43d4d88587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343686274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.343686274
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1442477908
Short name T385
Test name
Test status
Simulation time 1714364097 ps
CPU time 21.13 seconds
Started Mar 12 12:53:47 PM PDT 24
Finished Mar 12 12:54:09 PM PDT 24
Peak memory 196616 kb
Host smart-edef5fe5-5b6a-4b34-8f5f-fd41df5e3c60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442477908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1442477908
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3831811040
Short name T371
Test name
Test status
Simulation time 70082323 ps
CPU time 0.83 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 196108 kb
Host smart-b68a56fb-c674-4a8a-9866-5533dc63954c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831811040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3831811040
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2708137678
Short name T27
Test name
Test status
Simulation time 33193226 ps
CPU time 0.91 seconds
Started Mar 12 12:53:43 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 196340 kb
Host smart-653bde37-ac0f-46bc-b065-ec7f97fbf2bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708137678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2708137678
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3569584167
Short name T697
Test name
Test status
Simulation time 282021484 ps
CPU time 2.91 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 198184 kb
Host smart-6e772024-0f18-46cb-a792-c82501f82b3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569584167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3569584167
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.597103137
Short name T386
Test name
Test status
Simulation time 214916358 ps
CPU time 1.98 seconds
Started Mar 12 12:53:47 PM PDT 24
Finished Mar 12 12:53:50 PM PDT 24
Peak memory 196096 kb
Host smart-9cc774a1-6278-492e-a194-42efd1185f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597103137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
597103137
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4214891488
Short name T236
Test name
Test status
Simulation time 143481399 ps
CPU time 1 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 195980 kb
Host smart-61e07d07-2b9f-4616-9c05-67b00c4d07b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214891488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4214891488
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4268758112
Short name T280
Test name
Test status
Simulation time 24553395 ps
CPU time 0.72 seconds
Started Mar 12 12:53:53 PM PDT 24
Finished Mar 12 12:53:54 PM PDT 24
Peak memory 196092 kb
Host smart-04098212-091d-4afd-807f-adaf3479f267
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268758112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4268758112
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3546112442
Short name T259
Test name
Test status
Simulation time 134324242 ps
CPU time 3.08 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 198104 kb
Host smart-4d858d49-0df9-41af-a052-07f85612c83e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546112442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3546112442
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2755048726
Short name T600
Test name
Test status
Simulation time 63984297 ps
CPU time 1.28 seconds
Started Mar 12 12:53:53 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 196984 kb
Host smart-a0f8520f-5965-45ed-bcad-065242150e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755048726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2755048726
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.665749297
Short name T624
Test name
Test status
Simulation time 156677857 ps
CPU time 1.3 seconds
Started Mar 12 12:53:45 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 196860 kb
Host smart-ee9c6fd9-f5dd-4d76-a9dc-0b79fa2adf22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665749297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.665749297
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2074138842
Short name T274
Test name
Test status
Simulation time 2369992562 ps
CPU time 59.84 seconds
Started Mar 12 12:53:52 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 198316 kb
Host smart-b0900acf-49e3-4a4b-8e32-3442f9835ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074138842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2074138842
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3117712884
Short name T560
Test name
Test status
Simulation time 13231567 ps
CPU time 0.57 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 194244 kb
Host smart-8e6ffccf-863d-44c9-abba-b328519010cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117712884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3117712884
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2969965530
Short name T257
Test name
Test status
Simulation time 15370620 ps
CPU time 0.72 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 194248 kb
Host smart-cdb783fb-bd6b-430c-9baf-ed9e79c59632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969965530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2969965530
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2041741730
Short name T104
Test name
Test status
Simulation time 1308341507 ps
CPU time 15.05 seconds
Started Mar 12 12:53:45 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 197000 kb
Host smart-d6f2ce83-5303-4c47-a4c8-24d2d0c81913
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041741730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2041741730
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.670413616
Short name T693
Test name
Test status
Simulation time 34622164 ps
CPU time 0.72 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 194780 kb
Host smart-0e6bc2af-eaea-4bdc-a30b-c3cb54cf584c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670413616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.670413616
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3235020895
Short name T603
Test name
Test status
Simulation time 59152566 ps
CPU time 0.96 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 195972 kb
Host smart-b1a4ed67-ad44-4870-aa59-17aa407dfdd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235020895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3235020895
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2740087818
Short name T168
Test name
Test status
Simulation time 36632220 ps
CPU time 1.45 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196984 kb
Host smart-fedfdd8a-3ffa-47e9-857d-ecc2aa1f33d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740087818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2740087818
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.831478734
Short name T678
Test name
Test status
Simulation time 214382363 ps
CPU time 3.27 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 197204 kb
Host smart-f72c7f5e-eb31-462c-86f7-ebce8146910c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831478734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
831478734
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1463647531
Short name T108
Test name
Test status
Simulation time 29739699 ps
CPU time 1.05 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 196852 kb
Host smart-93d111e9-3748-4200-ae3b-4247d363a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463647531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1463647531
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3435837133
Short name T125
Test name
Test status
Simulation time 59849382 ps
CPU time 1.13 seconds
Started Mar 12 12:53:47 PM PDT 24
Finished Mar 12 12:53:49 PM PDT 24
Peak memory 196824 kb
Host smart-2f3d9bc9-6166-4a0d-b505-0ceb68e682c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435837133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3435837133
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3427881436
Short name T185
Test name
Test status
Simulation time 118479795 ps
CPU time 2.84 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:54 PM PDT 24
Peak memory 198056 kb
Host smart-2173c443-1e9d-4993-8bff-0bb40cf75800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427881436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3427881436
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1733605544
Short name T402
Test name
Test status
Simulation time 29816015 ps
CPU time 0.97 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196668 kb
Host smart-c223f2c1-b51d-461b-a73b-1333b446bc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733605544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1733605544
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3612159116
Short name T503
Test name
Test status
Simulation time 61545972 ps
CPU time 1.08 seconds
Started Mar 12 12:53:44 PM PDT 24
Finished Mar 12 12:53:46 PM PDT 24
Peak memory 195756 kb
Host smart-d5e79b2d-f6d8-4c93-b070-481865c157e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612159116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3612159116
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2985437416
Short name T369
Test name
Test status
Simulation time 17708226950 ps
CPU time 96.51 seconds
Started Mar 12 12:53:52 PM PDT 24
Finished Mar 12 12:55:29 PM PDT 24
Peak memory 198236 kb
Host smart-af192908-e9e4-43bf-b292-95ed1f8992c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985437416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2985437416
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.4112377358
Short name T59
Test name
Test status
Simulation time 372818732228 ps
CPU time 2112.32 seconds
Started Mar 12 12:53:41 PM PDT 24
Finished Mar 12 01:28:54 PM PDT 24
Peak memory 198456 kb
Host smart-cfb91bb2-23aa-4e50-9bb6-88e461d9c942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4112377358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.4112377358
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3329250834
Short name T156
Test name
Test status
Simulation time 12730304 ps
CPU time 0.59 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 194588 kb
Host smart-2bee352a-b88c-45ff-ad14-d10b6ea1a211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329250834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3329250834
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1365844030
Short name T338
Test name
Test status
Simulation time 178140314 ps
CPU time 0.75 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196072 kb
Host smart-fc48a67a-6158-4ada-97b5-4cab3e597293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365844030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1365844030
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1534017020
Short name T596
Test name
Test status
Simulation time 2331706309 ps
CPU time 22.32 seconds
Started Mar 12 12:54:04 PM PDT 24
Finished Mar 12 12:54:27 PM PDT 24
Peak memory 197200 kb
Host smart-9283e502-c074-4aac-8110-3e07c9a15023
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534017020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1534017020
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2451554123
Short name T139
Test name
Test status
Simulation time 77326140 ps
CPU time 0.57 seconds
Started Mar 12 12:53:49 PM PDT 24
Finished Mar 12 12:53:50 PM PDT 24
Peak memory 194356 kb
Host smart-eed2ffe3-f046-48b7-a6c3-6301534a3c67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451554123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2451554123
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3530484966
Short name T206
Test name
Test status
Simulation time 65439754 ps
CPU time 0.8 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:53:47 PM PDT 24
Peak memory 196152 kb
Host smart-e2a84aba-c2f2-4569-b874-77e15ebea9b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530484966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3530484966
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2777549646
Short name T18
Test name
Test status
Simulation time 57598177 ps
CPU time 2.21 seconds
Started Mar 12 12:53:48 PM PDT 24
Finished Mar 12 12:53:50 PM PDT 24
Peak memory 198248 kb
Host smart-9ece2cec-6365-403b-9933-2a8cf5ee7d96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777549646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2777549646
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3292578359
Short name T638
Test name
Test status
Simulation time 375190974 ps
CPU time 2.96 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 197156 kb
Host smart-b9a93633-a43a-4eed-b10a-b7c9ad88047d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292578359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3292578359
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1436698382
Short name T442
Test name
Test status
Simulation time 20332166 ps
CPU time 0.7 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 195444 kb
Host smart-05780f16-aa75-4066-8937-8bfe7ec9ef61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436698382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1436698382
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2449511007
Short name T475
Test name
Test status
Simulation time 175152093 ps
CPU time 0.94 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 196152 kb
Host smart-1ebb50b5-4244-4ec1-a55f-84068a62c95c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449511007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2449511007
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2399925204
Short name T224
Test name
Test status
Simulation time 548856735 ps
CPU time 4.61 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 198148 kb
Host smart-fecbe6b2-d1b5-4167-ba76-ca3b1c04dda4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399925204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2399925204
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.23805593
Short name T410
Test name
Test status
Simulation time 116561473 ps
CPU time 1.27 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:53 PM PDT 24
Peak memory 196876 kb
Host smart-29a016fc-8bdc-4877-9bad-b92f12f1c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23805593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.23805593
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4265543797
Short name T55
Test name
Test status
Simulation time 43133386 ps
CPU time 0.98 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 195532 kb
Host smart-0f89bf83-f644-4b41-b89a-c070490c775a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265543797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4265543797
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1937470034
Short name T401
Test name
Test status
Simulation time 10471305740 ps
CPU time 145.66 seconds
Started Mar 12 12:53:46 PM PDT 24
Finished Mar 12 12:56:11 PM PDT 24
Peak memory 198344 kb
Host smart-7bc0256d-b131-4846-b7b9-2eb7a3dc22bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937470034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1937470034
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.373320288
Short name T457
Test name
Test status
Simulation time 163399515711 ps
CPU time 1767.77 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 01:23:19 PM PDT 24
Peak memory 198492 kb
Host smart-460d8de9-02b7-4916-9df0-43bbb0d13f0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=373320288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.373320288
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3661353051
Short name T674
Test name
Test status
Simulation time 27828567 ps
CPU time 0.57 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 194792 kb
Host smart-2ab57aa2-cc23-49c9-aaba-964ccea68cd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661353051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3661353051
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.638159787
Short name T576
Test name
Test status
Simulation time 144418569 ps
CPU time 0.79 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 196168 kb
Host smart-15a04b2f-7f6e-49b4-8158-b67907f7f36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638159787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.638159787
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1951387678
Short name T647
Test name
Test status
Simulation time 2640570836 ps
CPU time 8.84 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 198324 kb
Host smart-2d169b14-2aa4-4900-bb1b-9005f3251fc6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951387678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1951387678
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2720655065
Short name T251
Test name
Test status
Simulation time 120591819 ps
CPU time 0.81 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 195976 kb
Host smart-703cee3c-45ca-454e-bef1-ffc6f740c1f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720655065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2720655065
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2529984925
Short name T298
Test name
Test status
Simulation time 93117218 ps
CPU time 1.26 seconds
Started Mar 12 12:54:03 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 197140 kb
Host smart-181fa771-16e1-4296-b05b-2d59405146f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529984925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2529984925
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2972787303
Short name T122
Test name
Test status
Simulation time 102917122 ps
CPU time 1.91 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 198168 kb
Host smart-7a37c60e-e3b4-41a3-886a-1b45cb391d16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972787303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2972787303
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3743314413
Short name T311
Test name
Test status
Simulation time 149973378 ps
CPU time 2.35 seconds
Started Mar 12 12:53:42 PM PDT 24
Finished Mar 12 12:53:44 PM PDT 24
Peak memory 198148 kb
Host smart-1c9c4cde-6d2a-4d5b-9eef-8734081660b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743314413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3743314413
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1579645072
Short name T631
Test name
Test status
Simulation time 42869207 ps
CPU time 0.66 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 195088 kb
Host smart-70d8c81e-35ca-45f2-8a87-c4e5b0a9d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579645072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1579645072
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2272256696
Short name T639
Test name
Test status
Simulation time 79165519 ps
CPU time 0.91 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 196708 kb
Host smart-74bd218f-fbd9-46e9-baf7-409977a8c428
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272256696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2272256696
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3950045290
Short name T293
Test name
Test status
Simulation time 163779123 ps
CPU time 3.87 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 198040 kb
Host smart-5ba33377-df17-4d52-b6a6-ec265e817b62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950045290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3950045290
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2557411592
Short name T12
Test name
Test status
Simulation time 93091476 ps
CPU time 0.94 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 196172 kb
Host smart-4f0181f0-af7c-44a3-b48d-501e68576edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557411592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2557411592
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.986882019
Short name T226
Test name
Test status
Simulation time 37729890 ps
CPU time 1.12 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 196672 kb
Host smart-d5975a80-bdf9-44ff-b046-e998d72c15fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986882019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.986882019
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1576806755
Short name T212
Test name
Test status
Simulation time 6755236715 ps
CPU time 162.42 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:56:41 PM PDT 24
Peak memory 198312 kb
Host smart-b81bebee-95d5-4a64-aa11-f7774063883d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576806755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1576806755
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.926886035
Short name T685
Test name
Test status
Simulation time 61636313942 ps
CPU time 741.6 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 01:06:17 PM PDT 24
Peak memory 198408 kb
Host smart-1b430471-39ad-4837-873a-8fb66576f135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=926886035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.926886035
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.454978200
Short name T581
Test name
Test status
Simulation time 19762997 ps
CPU time 0.55 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 194052 kb
Host smart-f2da5912-b0c9-4d6f-a462-a8724fe826b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454978200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.454978200
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.853830135
Short name T434
Test name
Test status
Simulation time 17385963 ps
CPU time 0.58 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 193984 kb
Host smart-3f2594a9-f64d-4c89-8695-b9ee9831c6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853830135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.853830135
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.188024387
Short name T164
Test name
Test status
Simulation time 3608124478 ps
CPU time 26.82 seconds
Started Mar 12 12:53:53 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 197576 kb
Host smart-44a712b7-fc37-47f4-9ca2-144d381a6082
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188024387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.188024387
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2923956185
Short name T177
Test name
Test status
Simulation time 286027431 ps
CPU time 0.94 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 197916 kb
Host smart-012cc57c-cc69-4389-ac5a-544456b63214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923956185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2923956185
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3886618509
Short name T483
Test name
Test status
Simulation time 197286678 ps
CPU time 1.23 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 197324 kb
Host smart-3209a3e4-6583-41a1-9e52-2b92c328ccf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886618509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3886618509
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3663096101
Short name T225
Test name
Test status
Simulation time 62077203 ps
CPU time 2.36 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 196396 kb
Host smart-b9337f6d-84c3-462a-9f02-65e65c5a44ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663096101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3663096101
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2623815451
Short name T667
Test name
Test status
Simulation time 584562440 ps
CPU time 1.37 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 196072 kb
Host smart-8d6e404c-8da9-4fd6-be99-51f02a37811a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623815451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2623815451
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1270772553
Short name T537
Test name
Test status
Simulation time 89458051 ps
CPU time 0.95 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 196176 kb
Host smart-a5568925-25e4-4f5e-91ae-475afd016c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270772553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1270772553
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4131340834
Short name T223
Test name
Test status
Simulation time 112958072 ps
CPU time 1.1 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 196932 kb
Host smart-f2ccdebe-eeab-4848-b7b8-2269ecc56829
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131340834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4131340834
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2839808081
Short name T688
Test name
Test status
Simulation time 85758407 ps
CPU time 3.99 seconds
Started Mar 12 12:53:52 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 198116 kb
Host smart-26ff1fab-53ba-40c0-a35a-12310dc068f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839808081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2839808081
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3708044373
Short name T428
Test name
Test status
Simulation time 57216551 ps
CPU time 0.8 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 195344 kb
Host smart-12f23441-b606-4665-9290-c4434f456190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708044373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3708044373
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.127162287
Short name T575
Test name
Test status
Simulation time 342772493 ps
CPU time 1.08 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 196408 kb
Host smart-c947ccd9-af36-43ed-8530-e7caff1b2e7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127162287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.127162287
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3292619677
Short name T543
Test name
Test status
Simulation time 237561141138 ps
CPU time 164.69 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:56:46 PM PDT 24
Peak memory 198332 kb
Host smart-301ce8b9-e92e-4033-8498-341d4d8d2055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292619677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3292619677
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.344207815
Short name T555
Test name
Test status
Simulation time 74470041380 ps
CPU time 1709.02 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 01:22:26 PM PDT 24
Peak memory 198492 kb
Host smart-49c24906-b7fe-4222-9ba4-a478974d393b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=344207815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.344207815
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1755448297
Short name T40
Test name
Test status
Simulation time 12466806 ps
CPU time 0.58 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 193980 kb
Host smart-bd82886d-8d30-47d6-91f2-3cd4237703e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755448297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1755448297
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2498961878
Short name T504
Test name
Test status
Simulation time 86518054 ps
CPU time 0.79 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 195616 kb
Host smart-4b58631a-f4e0-4a12-ac38-01a1cb1a5457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498961878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2498961878
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.224258510
Short name T712
Test name
Test status
Simulation time 531144116 ps
CPU time 27.45 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 197068 kb
Host smart-90b2035c-abbd-4a35-a2d4-953493f6740d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224258510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.224258510
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1943407502
Short name T24
Test name
Test status
Simulation time 54567446 ps
CPU time 0.88 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196096 kb
Host smart-f8764365-3d63-4bd7-a27c-8c22379b2889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943407502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1943407502
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3896202368
Short name T635
Test name
Test status
Simulation time 238916497 ps
CPU time 0.89 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 196676 kb
Host smart-1a0a2d6b-2f62-4923-a773-e0552f54662b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896202368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3896202368
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1003435862
Short name T474
Test name
Test status
Simulation time 69500838 ps
CPU time 1.88 seconds
Started Mar 12 12:54:04 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 198120 kb
Host smart-faa25b94-b517-4db6-a195-6c1573ce4ec5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003435862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1003435862
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.623831801
Short name T159
Test name
Test status
Simulation time 329053624 ps
CPU time 2.1 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 196216 kb
Host smart-8025c3a3-e0cf-49df-853a-849ad2e7824b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623831801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
623831801
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4090204875
Short name T219
Test name
Test status
Simulation time 71496104 ps
CPU time 0.9 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 195872 kb
Host smart-c196df29-fcc8-4781-85be-167c1d3c4df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090204875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4090204875
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.957839457
Short name T194
Test name
Test status
Simulation time 98240411 ps
CPU time 0.71 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 195460 kb
Host smart-2ec651c5-b38f-4af7-8227-e915a12af432
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957839457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.957839457
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4095036202
Short name T287
Test name
Test status
Simulation time 279138660 ps
CPU time 4.29 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 198148 kb
Host smart-4961c24a-3ede-4489-afdd-26ef9e6d44da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095036202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4095036202
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3515270434
Short name T99
Test name
Test status
Simulation time 41997325 ps
CPU time 0.95 seconds
Started Mar 12 12:53:51 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 196172 kb
Host smart-6528f18f-eb57-4ddb-a14f-24d8eafdb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515270434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3515270434
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3273535343
Short name T315
Test name
Test status
Simulation time 87772570 ps
CPU time 1.44 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 198048 kb
Host smart-a523c2d7-ad1a-4d51-a594-d8a57b6af174
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273535343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3273535343
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1218208293
Short name T383
Test name
Test status
Simulation time 14386268458 ps
CPU time 187.72 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:57:03 PM PDT 24
Peak memory 198292 kb
Host smart-e5f52d33-f5c6-4cbf-affc-a57bf2640881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218208293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1218208293
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1483476813
Short name T404
Test name
Test status
Simulation time 48758327 ps
CPU time 0.57 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 194240 kb
Host smart-6a0e4559-0dd7-443a-9e43-11725e2d5ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483476813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1483476813
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2973353656
Short name T672
Test name
Test status
Simulation time 30498467 ps
CPU time 0.85 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 195768 kb
Host smart-ccbb6070-188c-4a48-9fd7-df86f2ff621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973353656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2973353656
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3237169835
Short name T126
Test name
Test status
Simulation time 1186375785 ps
CPU time 21.51 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 197140 kb
Host smart-22e3164e-e166-40a1-9835-0fc7320d310f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237169835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3237169835
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3411464655
Short name T675
Test name
Test status
Simulation time 108354892 ps
CPU time 0.87 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 197344 kb
Host smart-d76f52d9-6329-47fc-b13e-db08df230cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411464655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3411464655
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.140956215
Short name T485
Test name
Test status
Simulation time 358663029 ps
CPU time 1.4 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:08 PM PDT 24
Peak memory 195988 kb
Host smart-c0ab20c3-9560-4589-997b-3e28fa6a4d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140956215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.140956215
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1135172893
Short name T592
Test name
Test status
Simulation time 28515103 ps
CPU time 1.32 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 196720 kb
Host smart-921ac1c2-ac78-41c8-b902-639dbefeec2b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135172893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1135172893
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4263511671
Short name T353
Test name
Test status
Simulation time 234159995 ps
CPU time 2.49 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 197028 kb
Host smart-8ac59558-425e-46a2-ab6d-ee30fab08944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263511671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4263511671
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.453613143
Short name T626
Test name
Test status
Simulation time 23721282 ps
CPU time 0.86 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 196152 kb
Host smart-dea7cd9a-e06a-4d5f-a06c-6376295be354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453613143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.453613143
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1797833849
Short name T127
Test name
Test status
Simulation time 156812453 ps
CPU time 0.99 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 195940 kb
Host smart-e28437aa-7348-4a92-89e4-123fc53693f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797833849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1797833849
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3156736397
Short name T103
Test name
Test status
Simulation time 1112419992 ps
CPU time 5.79 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 198048 kb
Host smart-1adc560c-f504-4117-8130-24dd504b622a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156736397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3156736397
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.104386625
Short name T56
Test name
Test status
Simulation time 222129262 ps
CPU time 1.01 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 196384 kb
Host smart-039bea2b-5a23-490a-af6d-757d39eae5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104386625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.104386625
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3825270257
Short name T153
Test name
Test status
Simulation time 67241933 ps
CPU time 1.12 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 195788 kb
Host smart-0aa8a447-c578-46cb-ae1a-6cdd2f6a5cec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825270257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3825270257
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.977096390
Short name T440
Test name
Test status
Simulation time 7522414561 ps
CPU time 103.46 seconds
Started Mar 12 12:54:10 PM PDT 24
Finished Mar 12 12:55:54 PM PDT 24
Peak memory 197620 kb
Host smart-f6cb215d-1d4f-4fe6-a5e1-a6f1473d5ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977096390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.977096390
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.481123172
Short name T49
Test name
Test status
Simulation time 44941017 ps
CPU time 0.56 seconds
Started Mar 12 12:52:52 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 194256 kb
Host smart-237e4226-88c3-4745-a3b1-bff4604dcd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481123172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.481123172
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2890417105
Short name T593
Test name
Test status
Simulation time 21553858 ps
CPU time 0.71 seconds
Started Mar 12 12:52:51 PM PDT 24
Finished Mar 12 12:52:52 PM PDT 24
Peak memory 195928 kb
Host smart-122ff273-a4d4-43ea-b60b-19ad899265e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890417105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2890417105
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2735680285
Short name T330
Test name
Test status
Simulation time 274369001 ps
CPU time 3.51 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 196076 kb
Host smart-b89b6847-e0c7-47a1-a6f7-303afb7459b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735680285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2735680285
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4128448859
Short name T602
Test name
Test status
Simulation time 56729807 ps
CPU time 0.71 seconds
Started Mar 12 12:53:11 PM PDT 24
Finished Mar 12 12:53:13 PM PDT 24
Peak memory 195452 kb
Host smart-d9cc80d8-869c-4100-a567-82da5fd95a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128448859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4128448859
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1145971473
Short name T544
Test name
Test status
Simulation time 252207438 ps
CPU time 1.17 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 196300 kb
Host smart-90b85e22-ce2a-42fd-987f-75c1b106da99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145971473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1145971473
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2911832210
Short name T187
Test name
Test status
Simulation time 242846138 ps
CPU time 2.5 seconds
Started Mar 12 12:52:59 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 198092 kb
Host smart-4b002e6a-7425-4230-a685-b047dca57cc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911832210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2911832210
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3220652892
Short name T588
Test name
Test status
Simulation time 72203455 ps
CPU time 2.07 seconds
Started Mar 12 12:52:58 PM PDT 24
Finished Mar 12 12:53:00 PM PDT 24
Peak memory 197216 kb
Host smart-b830cbf1-731b-422c-bafe-7fb56fb0c236
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220652892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3220652892
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.301116920
Short name T252
Test name
Test status
Simulation time 99584879 ps
CPU time 0.97 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196648 kb
Host smart-3e092f48-9845-4bfa-81f0-0408e3d08e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301116920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.301116920
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1846288003
Short name T282
Test name
Test status
Simulation time 39636447 ps
CPU time 0.96 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 195852 kb
Host smart-220be0a0-da00-4688-a404-94cea684ec15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846288003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1846288003
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.437724606
Short name T451
Test name
Test status
Simulation time 535661059 ps
CPU time 6.09 seconds
Started Mar 12 12:52:53 PM PDT 24
Finished Mar 12 12:52:59 PM PDT 24
Peak memory 198092 kb
Host smart-bb1250b0-8ec5-49ec-9bc5-49faff9298dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437724606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.437724606
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2154109613
Short name T51
Test name
Test status
Simulation time 415288326 ps
CPU time 0.94 seconds
Started Mar 12 12:52:55 PM PDT 24
Finished Mar 12 12:52:56 PM PDT 24
Peak memory 213772 kb
Host smart-1a9ae00f-3e25-40cc-95a9-b64aa00655d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154109613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2154109613
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1546310085
Short name T613
Test name
Test status
Simulation time 51023758 ps
CPU time 0.91 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 195904 kb
Host smart-823abe60-eb78-4530-9d6a-1a2ed9f205aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546310085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1546310085
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1839311093
Short name T670
Test name
Test status
Simulation time 44377617 ps
CPU time 1.2 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 195640 kb
Host smart-8120d0f0-257b-4ff9-a881-6ee48ecdaa78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839311093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1839311093
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2953558452
Short name T20
Test name
Test status
Simulation time 176395567827 ps
CPU time 139.67 seconds
Started Mar 12 12:53:17 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 198264 kb
Host smart-a2915af8-27ed-4208-8ffc-a9dd69a62e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953558452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2953558452
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1836169393
Short name T454
Test name
Test status
Simulation time 21959494 ps
CPU time 0.58 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 194060 kb
Host smart-fea0e164-b15c-4906-ac68-1dc2b7b9aa66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836169393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1836169393
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2562176404
Short name T470
Test name
Test status
Simulation time 90224639 ps
CPU time 0.65 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 194216 kb
Host smart-56bc2f44-ebee-4c48-b353-89168899f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562176404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2562176404
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.397506196
Short name T506
Test name
Test status
Simulation time 1273072653 ps
CPU time 8.34 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 197088 kb
Host smart-b541ffe2-ca04-46e3-a26e-fe49b5d5d682
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397506196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.397506196
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2326870107
Short name T21
Test name
Test status
Simulation time 91627141 ps
CPU time 0.95 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 196964 kb
Host smart-a9663e1c-996e-419f-a66f-489c5169f5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326870107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2326870107
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2637885551
Short name T188
Test name
Test status
Simulation time 67949157 ps
CPU time 1.17 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 196616 kb
Host smart-7569f62d-bad6-45d0-9862-1c753a84aa1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637885551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2637885551
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1202185152
Short name T379
Test name
Test status
Simulation time 37328231 ps
CPU time 1.34 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 196424 kb
Host smart-2256f14c-f957-4358-b4c0-fca8f013bd7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202185152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1202185152
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.248715824
Short name T144
Test name
Test status
Simulation time 147878925 ps
CPU time 0.99 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 195524 kb
Host smart-02bacafa-6119-4816-9afb-7768ab485a34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248715824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
248715824
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2544693416
Short name T480
Test name
Test status
Simulation time 51507719 ps
CPU time 0.77 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196364 kb
Host smart-4864742f-11b7-4c54-9a9f-3a13f83085db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544693416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2544693416
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2579417653
Short name T289
Test name
Test status
Simulation time 92913287 ps
CPU time 1.2 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 197164 kb
Host smart-069967b8-815b-4d9e-b519-97cfeec5bf3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579417653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2579417653
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3372754580
Short name T687
Test name
Test status
Simulation time 857759989 ps
CPU time 2.96 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 198004 kb
Host smart-02510550-05d2-4dc0-bb91-6e7e1967c17f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372754580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3372754580
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2192748088
Short name T591
Test name
Test status
Simulation time 46439793 ps
CPU time 1.22 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 196572 kb
Host smart-0b58c9dd-73df-4865-b344-26bb06018108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192748088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2192748088
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3353115292
Short name T651
Test name
Test status
Simulation time 45223285 ps
CPU time 1.16 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 196688 kb
Host smart-220fcb44-37a4-47b4-994b-f3d9ab41a778
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353115292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3353115292
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2022746262
Short name T8
Test name
Test status
Simulation time 74565360785 ps
CPU time 188.85 seconds
Started Mar 12 12:54:04 PM PDT 24
Finished Mar 12 12:57:13 PM PDT 24
Peak memory 198312 kb
Host smart-ce19d9c4-7e4c-406b-9593-6d886c464dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022746262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2022746262
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3027110814
Short name T387
Test name
Test status
Simulation time 45134861 ps
CPU time 0.57 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 194060 kb
Host smart-9d02e308-5063-4a34-b0c8-79532e490786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027110814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3027110814
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1725435323
Short name T102
Test name
Test status
Simulation time 91433307 ps
CPU time 0.78 seconds
Started Mar 12 12:54:03 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 195300 kb
Host smart-469933b9-26bf-4391-910c-15c6f4d9e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725435323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1725435323
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3850849142
Short name T612
Test name
Test status
Simulation time 155964491 ps
CPU time 4.56 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 196100 kb
Host smart-c9a9c810-8e5f-4fb1-9e20-7569296fed62
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850849142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3850849142
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4117719040
Short name T448
Test name
Test status
Simulation time 217160530 ps
CPU time 1.09 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 196388 kb
Host smart-959c7b2f-5a86-4f57-a725-fe51a1cde138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117719040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4117719040
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.925914458
Short name T533
Test name
Test status
Simulation time 48214731 ps
CPU time 0.93 seconds
Started Mar 12 12:54:03 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 196864 kb
Host smart-e3109938-620f-4b84-91cf-7a0c6862d5fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925914458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.925914458
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.402455510
Short name T356
Test name
Test status
Simulation time 53810757 ps
CPU time 1.33 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 198012 kb
Host smart-acd54c1d-ba8f-448d-8180-878e66ad6b02
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402455510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.402455510
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1214646973
Short name T277
Test name
Test status
Simulation time 129115803 ps
CPU time 2.18 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 197208 kb
Host smart-e49540b3-aa56-4e6e-a4a2-29b0c20a2a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214646973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1214646973
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3912822169
Short name T334
Test name
Test status
Simulation time 34990241 ps
CPU time 1.14 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 195972 kb
Host smart-d81e27d5-759f-4501-9a8f-2896dd556e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912822169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3912822169
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4137563103
Short name T513
Test name
Test status
Simulation time 621649351 ps
CPU time 0.83 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 196524 kb
Host smart-3541e4fd-1100-4ff0-9a93-2fb24679bea5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137563103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4137563103
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3003433090
Short name T530
Test name
Test status
Simulation time 373088897 ps
CPU time 2.05 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 198120 kb
Host smart-4c1e97d5-3ecb-4c3a-8db2-54dba7349def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003433090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3003433090
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.210181222
Short name T679
Test name
Test status
Simulation time 236413859 ps
CPU time 1.11 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 196596 kb
Host smart-ec2fd5b0-4960-4c64-8520-723288eb3e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210181222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.210181222
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1696410334
Short name T106
Test name
Test status
Simulation time 87657027 ps
CPU time 1.26 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 195688 kb
Host smart-f257b598-2ba5-4bc8-8016-877f1dcc236e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696410334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1696410334
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3231208052
Short name T376
Test name
Test status
Simulation time 27843019311 ps
CPU time 134.1 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 198280 kb
Host smart-1f6f9a75-fa70-4e67-ae66-a05561ac21da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231208052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3231208052
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.4014852705
Short name T611
Test name
Test status
Simulation time 82951568 ps
CPU time 0.56 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 193540 kb
Host smart-9e973afa-c43e-47be-b238-c3e96e6154f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014852705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4014852705
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.455695829
Short name T279
Test name
Test status
Simulation time 72816181 ps
CPU time 0.71 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:57 PM PDT 24
Peak memory 194108 kb
Host smart-737fcd92-2b39-4ee0-939b-2724401ea860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455695829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.455695829
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.333056794
Short name T320
Test name
Test status
Simulation time 329473167 ps
CPU time 16.05 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:54:12 PM PDT 24
Peak memory 196392 kb
Host smart-3bfc0017-ac4e-471d-89c2-c7cff551a063
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333056794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.333056794
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1923635255
Short name T608
Test name
Test status
Simulation time 141324815 ps
CPU time 0.75 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 195920 kb
Host smart-13894d7d-1e83-44ee-99d3-fcba30d425ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923635255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1923635255
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.110436068
Short name T247
Test name
Test status
Simulation time 154969318 ps
CPU time 1.28 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 197324 kb
Host smart-cd93acb9-dc26-4862-8645-fbf4b78e82c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110436068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.110436068
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2919445865
Short name T217
Test name
Test status
Simulation time 265084667 ps
CPU time 2.64 seconds
Started Mar 12 12:53:56 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 196416 kb
Host smart-941afaa1-b48b-467d-a4b5-5d7697b1a82f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919445865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2919445865
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2413434110
Short name T525
Test name
Test status
Simulation time 195588175 ps
CPU time 1.27 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196956 kb
Host smart-6816500c-6232-4657-8d4e-2e271d59fa5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413434110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2413434110
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2981668613
Short name T465
Test name
Test status
Simulation time 36807618 ps
CPU time 0.95 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196044 kb
Host smart-ec810c7d-df0a-44dd-98d4-4169c966e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981668613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2981668613
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3030681844
Short name T395
Test name
Test status
Simulation time 48988834 ps
CPU time 0.94 seconds
Started Mar 12 12:53:54 PM PDT 24
Finished Mar 12 12:53:55 PM PDT 24
Peak memory 196900 kb
Host smart-ddce7473-35b8-4a01-8988-ac2394369a25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030681844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3030681844
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2918004060
Short name T507
Test name
Test status
Simulation time 307575415 ps
CPU time 2.07 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 198184 kb
Host smart-9f80c935-83a4-45bc-b96e-8e434e1f44c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918004060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2918004060
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2681216734
Short name T524
Test name
Test status
Simulation time 77646556 ps
CPU time 0.96 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 195836 kb
Host smart-f772a06d-b34f-4cab-bdee-98b7f7ae5ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681216734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2681216734
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.862193939
Short name T307
Test name
Test status
Simulation time 117263446 ps
CPU time 1.16 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 195576 kb
Host smart-4652c3c4-5d07-4e97-8e2b-7f0008921ed8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862193939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.862193939
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3194074535
Short name T682
Test name
Test status
Simulation time 7803028328 ps
CPU time 85.69 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:55:32 PM PDT 24
Peak memory 198324 kb
Host smart-7eb6b6d3-f8f6-4d89-be59-6411cce3ca5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194074535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3194074535
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3691085481
Short name T690
Test name
Test status
Simulation time 33780482 ps
CPU time 0.56 seconds
Started Mar 12 12:53:58 PM PDT 24
Finished Mar 12 12:53:59 PM PDT 24
Peak memory 194816 kb
Host smart-473ddc64-e5ec-4973-bc7d-141ba5a9fb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691085481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3691085481
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3465868576
Short name T169
Test name
Test status
Simulation time 67540682 ps
CPU time 0.88 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 197292 kb
Host smart-fdce3cd6-0769-499a-80ee-7cb2ec6fc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465868576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3465868576
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3544896732
Short name T271
Test name
Test status
Simulation time 826963144 ps
CPU time 4.17 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:05 PM PDT 24
Peak memory 196128 kb
Host smart-5536e0f9-3ae7-4687-9253-97b7c22a5f36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544896732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3544896732
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1640472346
Short name T468
Test name
Test status
Simulation time 383293248 ps
CPU time 0.98 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196780 kb
Host smart-f97d2f92-727b-44b5-b1d1-79fc63691546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640472346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1640472346
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.873254959
Short name T111
Test name
Test status
Simulation time 28891176 ps
CPU time 0.77 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 196296 kb
Host smart-490d6565-68f2-4703-864f-59812048a51f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873254959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.873254959
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3626465254
Short name T482
Test name
Test status
Simulation time 136936127 ps
CPU time 3.22 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 198204 kb
Host smart-6fa1d6f9-d2ef-4b33-a1df-a152df97dd2b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626465254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3626465254
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2760788916
Short name T515
Test name
Test status
Simulation time 272616608 ps
CPU time 1.96 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 196868 kb
Host smart-d8c30ea8-058d-4687-8450-a85ee04721a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760788916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2760788916
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2949561752
Short name T455
Test name
Test status
Simulation time 114875976 ps
CPU time 0.79 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196412 kb
Host smart-5ad1b245-e260-48d5-97b5-f729e6c0655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949561752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2949561752
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.976070886
Short name T614
Test name
Test status
Simulation time 32596719 ps
CPU time 0.68 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 194332 kb
Host smart-1d735885-1c33-4426-b801-b0067d660e41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976070886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.976070886
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1473480962
Short name T716
Test name
Test status
Simulation time 366459846 ps
CPU time 1.34 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 12:54:02 PM PDT 24
Peak memory 198184 kb
Host smart-1235306f-b04a-4d69-b633-edbdb293d776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473480962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1473480962
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1909585496
Short name T256
Test name
Test status
Simulation time 46832587 ps
CPU time 1.25 seconds
Started Mar 12 12:54:03 PM PDT 24
Finished Mar 12 12:54:05 PM PDT 24
Peak memory 196544 kb
Host smart-b5af9246-97a8-48fc-84fd-0113e6950cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909585496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1909585496
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4086032642
Short name T523
Test name
Test status
Simulation time 150599540 ps
CPU time 1.22 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:05 PM PDT 24
Peak memory 198108 kb
Host smart-1ad2dda7-d86f-4617-a5da-9332060b5c26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086032642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4086032642
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3589618239
Short name T135
Test name
Test status
Simulation time 119860870285 ps
CPU time 155.16 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:56:37 PM PDT 24
Peak memory 198272 kb
Host smart-71b14651-fa27-4912-a611-18e8040d2242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589618239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3589618239
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1523990252
Short name T65
Test name
Test status
Simulation time 81331153320 ps
CPU time 2182.64 seconds
Started Mar 12 12:54:01 PM PDT 24
Finished Mar 12 01:30:24 PM PDT 24
Peak memory 198408 kb
Host smart-f70f9c16-57e2-461d-859d-87f1d54b3e2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1523990252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1523990252
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.419910915
Short name T642
Test name
Test status
Simulation time 14523057 ps
CPU time 0.58 seconds
Started Mar 12 12:54:16 PM PDT 24
Finished Mar 12 12:54:17 PM PDT 24
Peak memory 194052 kb
Host smart-daa74710-572e-4076-860c-289b9347d077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419910915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.419910915
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3558715056
Short name T556
Test name
Test status
Simulation time 34626072 ps
CPU time 0.77 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 195568 kb
Host smart-43fcb7aa-f991-43f1-8eb4-f848f0551dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558715056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3558715056
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2240583008
Short name T542
Test name
Test status
Simulation time 460011777 ps
CPU time 22.55 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 198136 kb
Host smart-df6a9c95-9a7c-470a-808c-080e09241838
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240583008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2240583008
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.550558994
Short name T566
Test name
Test status
Simulation time 200995944 ps
CPU time 0.83 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:11 PM PDT 24
Peak memory 195892 kb
Host smart-a79caa15-9299-4a48-ba28-cb2ca346b5c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550558994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.550558994
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.19139058
Short name T433
Test name
Test status
Simulation time 185958339 ps
CPU time 1.41 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 198148 kb
Host smart-688b6460-e21a-4a7f-8930-ab32b58b9175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.19139058
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3289378424
Short name T487
Test name
Test status
Simulation time 62194368 ps
CPU time 2.26 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:14 PM PDT 24
Peak memory 196540 kb
Host smart-e7a27aa3-5f31-4b62-ba78-244c79b3d0a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289378424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3289378424
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1156715972
Short name T172
Test name
Test status
Simulation time 286242086 ps
CPU time 2.01 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 197168 kb
Host smart-bb7b05dc-79e6-491e-a700-0c5f29b9d0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156715972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1156715972
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3985738001
Short name T659
Test name
Test status
Simulation time 261714793 ps
CPU time 1.21 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 195992 kb
Host smart-521de2f2-86d1-4e9e-92b2-40bdc441a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985738001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3985738001
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3134013003
Short name T143
Test name
Test status
Simulation time 285120013 ps
CPU time 1.02 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196160 kb
Host smart-1b2a7fec-5de3-4af7-a70f-0b9c4e177643
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134013003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3134013003
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.690898868
Short name T337
Test name
Test status
Simulation time 762232493 ps
CPU time 2.45 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 198152 kb
Host smart-74fe81c9-50e3-4f7a-a498-e724513e9dcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690898868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.690898868
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.141509062
Short name T253
Test name
Test status
Simulation time 107745610 ps
CPU time 1.35 seconds
Started Mar 12 12:53:55 PM PDT 24
Finished Mar 12 12:53:56 PM PDT 24
Peak memory 198076 kb
Host smart-3ce50bea-afa4-47c1-a86c-3fbd25a8059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141509062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.141509062
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3848655772
Short name T628
Test name
Test status
Simulation time 55653162 ps
CPU time 1.24 seconds
Started Mar 12 12:53:57 PM PDT 24
Finished Mar 12 12:53:58 PM PDT 24
Peak memory 195896 kb
Host smart-ef67f451-dadc-4bbb-9ec3-29a313c96131
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848655772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3848655772
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.299095674
Short name T234
Test name
Test status
Simulation time 1525926855 ps
CPU time 23.13 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:25 PM PDT 24
Peak memory 198176 kb
Host smart-0c67080f-933d-40ae-9a53-386ec8e5ae1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299095674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.299095674
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1446399204
Short name T532
Test name
Test status
Simulation time 191810904710 ps
CPU time 625.61 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 01:04:31 PM PDT 24
Peak memory 198456 kb
Host smart-6497527d-a3d4-41a8-ac45-9b6fd75d30b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1446399204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1446399204
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.708983121
Short name T394
Test name
Test status
Simulation time 16963168 ps
CPU time 0.61 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 194192 kb
Host smart-4d265cd1-5ad1-48d1-8adf-9ad0ffee0aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708983121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.708983121
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.636895156
Short name T389
Test name
Test status
Simulation time 85159532 ps
CPU time 0.67 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 194212 kb
Host smart-6794c7fe-bea1-41ae-885d-5bd6b79d9e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636895156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.636895156
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.412087587
Short name T432
Test name
Test status
Simulation time 973705245 ps
CPU time 11.48 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 195592 kb
Host smart-ac7f98c4-0244-44fc-b6a4-cf42b7ad2e90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412087587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.412087587
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2914528138
Short name T145
Test name
Test status
Simulation time 364859098 ps
CPU time 1.03 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 196600 kb
Host smart-47bded36-1904-41ce-bade-6dfa993f8a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914528138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2914528138
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3361274005
Short name T706
Test name
Test status
Simulation time 57625882 ps
CPU time 1.06 seconds
Started Mar 12 12:54:15 PM PDT 24
Finished Mar 12 12:54:16 PM PDT 24
Peak memory 196268 kb
Host smart-7d2b1b4c-6e84-472e-b5fa-17a41140d302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361274005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3361274005
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1489529826
Short name T694
Test name
Test status
Simulation time 56631342 ps
CPU time 2.25 seconds
Started Mar 12 12:54:10 PM PDT 24
Finished Mar 12 12:54:13 PM PDT 24
Peak memory 197400 kb
Host smart-dd9b5852-2471-484d-adec-8c5728815df4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489529826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1489529826
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.747315611
Short name T539
Test name
Test status
Simulation time 144180612 ps
CPU time 1.13 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 196412 kb
Host smart-5e5da82f-b052-4f98-8376-21429b8445c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747315611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
747315611
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2326328441
Short name T686
Test name
Test status
Simulation time 19279864 ps
CPU time 0.68 seconds
Started Mar 12 12:54:08 PM PDT 24
Finished Mar 12 12:54:08 PM PDT 24
Peak memory 195092 kb
Host smart-c66a6a98-c5b0-417b-a1c9-c1aef6c7fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326328441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2326328441
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3297323049
Short name T516
Test name
Test status
Simulation time 258470654 ps
CPU time 1.07 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 196520 kb
Host smart-3e19c014-3bf2-471b-bc83-efad6466c7f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297323049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3297323049
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4378043
Short name T6
Test name
Test status
Simulation time 1305536990 ps
CPU time 2.56 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 197796 kb
Host smart-0e41b650-40df-4b9b-8d77-3cc3c7db81c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4378043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rando
m_long_reg_writes_reg_reads.4378043
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2316935791
Short name T578
Test name
Test status
Simulation time 132495949 ps
CPU time 0.99 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:11 PM PDT 24
Peak memory 195948 kb
Host smart-fc90ae1c-6645-49c2-ab2a-7fa1c29ba443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316935791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2316935791
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3867440642
Short name T552
Test name
Test status
Simulation time 149768159 ps
CPU time 0.83 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 195220 kb
Host smart-e2d30adf-6e92-431a-9cec-5eba8a3b61b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867440642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3867440642
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2331169314
Short name T58
Test name
Test status
Simulation time 19466128341 ps
CPU time 100.66 seconds
Started Mar 12 12:54:06 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 198236 kb
Host smart-ae89d096-2919-449b-b97e-786d82b0954c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331169314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2331169314
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3226012190
Short name T198
Test name
Test status
Simulation time 11271774 ps
CPU time 0.55 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:13 PM PDT 24
Peak memory 194692 kb
Host smart-8143ae52-0444-4e66-81a0-f9c2c507780d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226012190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3226012190
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3124388778
Short name T278
Test name
Test status
Simulation time 75321857 ps
CPU time 0.72 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 195140 kb
Host smart-8350d04b-b633-431e-b74c-0960ae8df7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124388778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3124388778
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2652001077
Short name T673
Test name
Test status
Simulation time 322907890 ps
CPU time 16.92 seconds
Started Mar 12 12:54:17 PM PDT 24
Finished Mar 12 12:54:34 PM PDT 24
Peak memory 196408 kb
Host smart-3e348031-f8c0-4ce7-94ad-11b003a44753
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652001077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2652001077
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1988797850
Short name T562
Test name
Test status
Simulation time 25751202 ps
CPU time 0.72 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:10 PM PDT 24
Peak memory 194904 kb
Host smart-fb026c73-e5f7-4aac-a088-4289bf404a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988797850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1988797850
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3675572170
Short name T572
Test name
Test status
Simulation time 195454899 ps
CPU time 1.06 seconds
Started Mar 12 12:53:59 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 195884 kb
Host smart-a4813d25-c537-43f8-a555-f8be5eb178d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675572170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3675572170
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.845453307
Short name T238
Test name
Test status
Simulation time 179488464 ps
CPU time 1.88 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:54:11 PM PDT 24
Peak memory 197724 kb
Host smart-1f47ea86-d8d8-4e9e-a57d-e7c6dd4f2e1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845453307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.845453307
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2608078041
Short name T203
Test name
Test status
Simulation time 470659640 ps
CPU time 3.26 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 197152 kb
Host smart-6caf7184-b2ca-4192-866f-88a56708382b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608078041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2608078041
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.179603267
Short name T595
Test name
Test status
Simulation time 743422757 ps
CPU time 1.06 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 196868 kb
Host smart-b9eb1e12-e239-4b03-ba0d-ecdffedb3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179603267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.179603267
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2774859557
Short name T358
Test name
Test status
Simulation time 45046985 ps
CPU time 0.64 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 194280 kb
Host smart-0f4134dc-41bc-4b15-9d9f-22337da3b29f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774859557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2774859557
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1572599537
Short name T571
Test name
Test status
Simulation time 231343052 ps
CPU time 5.15 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:08 PM PDT 24
Peak memory 198136 kb
Host smart-337e9e59-2ec4-4b1e-a429-2c68620521f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572599537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1572599537
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3032902896
Short name T676
Test name
Test status
Simulation time 48542312 ps
CPU time 1.22 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 195896 kb
Host smart-56116f4c-650e-4ee4-8fb2-1a4edff07b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032902896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3032902896
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3104215188
Short name T423
Test name
Test status
Simulation time 24235194 ps
CPU time 0.8 seconds
Started Mar 12 12:54:02 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 195204 kb
Host smart-5c4eeece-9724-4537-abd2-820b77ffe864
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104215188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3104215188
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4175443620
Short name T420
Test name
Test status
Simulation time 1917426840 ps
CPU time 50.84 seconds
Started Mar 12 12:54:09 PM PDT 24
Finished Mar 12 12:55:00 PM PDT 24
Peak memory 198152 kb
Host smart-81197e39-0753-4885-85da-5ce1c363baf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175443620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4175443620
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3586323406
Short name T443
Test name
Test status
Simulation time 34043576 ps
CPU time 0.6 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 194240 kb
Host smart-58486065-9d3a-4357-b24c-0913fc5e116d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586323406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3586323406
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1885863069
Short name T705
Test name
Test status
Simulation time 179966673 ps
CPU time 0.79 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 195456 kb
Host smart-95d0ab90-8dfb-4468-8cef-20da7dcf2456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885863069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1885863069
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.79648545
Short name T668
Test name
Test status
Simulation time 815764679 ps
CPU time 13.99 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 198148 kb
Host smart-fe1eb681-76a3-4e7a-a8fa-822ac922c1ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79648545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stress
.79648545
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2475258447
Short name T495
Test name
Test status
Simulation time 122307310 ps
CPU time 0.94 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 197832 kb
Host smart-c3afd043-de9a-4a71-ada6-089936cbdd8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475258447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2475258447
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1019271598
Short name T184
Test name
Test status
Simulation time 43885262 ps
CPU time 0.93 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 197312 kb
Host smart-556b5f71-d2a4-4a7e-9c8c-ae20e2362aa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019271598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1019271598
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1157186220
Short name T398
Test name
Test status
Simulation time 279538422 ps
CPU time 1.83 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:26 PM PDT 24
Peak memory 198112 kb
Host smart-12dcbcda-3081-4edf-9646-e4643094855f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157186220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1157186220
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.375224762
Short name T710
Test name
Test status
Simulation time 141241799 ps
CPU time 2.19 seconds
Started Mar 12 12:54:25 PM PDT 24
Finished Mar 12 12:54:28 PM PDT 24
Peak memory 198108 kb
Host smart-cac42be4-4ffe-4b37-85a5-8dbf8ac83ac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375224762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
375224762
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2802301885
Short name T567
Test name
Test status
Simulation time 52909177 ps
CPU time 1.13 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:07 PM PDT 24
Peak memory 197192 kb
Host smart-ff7e558d-05de-414a-a330-0be3ec9eafab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802301885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2802301885
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3614575660
Short name T411
Test name
Test status
Simulation time 63319477 ps
CPU time 0.66 seconds
Started Mar 12 12:54:05 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 195160 kb
Host smart-0fe20f4a-90ab-40c5-8a3f-01c15c24f106
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614575660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3614575660
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2171956491
Short name T654
Test name
Test status
Simulation time 1358201038 ps
CPU time 3.2 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 198112 kb
Host smart-423dc252-be69-4e67-8f23-451aaabb5daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171956491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2171956491
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.121305232
Short name T129
Test name
Test status
Simulation time 183465511 ps
CPU time 0.98 seconds
Started Mar 12 12:54:03 PM PDT 24
Finished Mar 12 12:54:04 PM PDT 24
Peak memory 196356 kb
Host smart-08cc8c47-0842-4ed4-af7d-871aa991fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121305232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.121305232
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.339562927
Short name T645
Test name
Test status
Simulation time 262605039 ps
CPU time 1.25 seconds
Started Mar 12 12:54:00 PM PDT 24
Finished Mar 12 12:54:01 PM PDT 24
Peak memory 196848 kb
Host smart-fcfde6a1-166a-4bef-8dbf-fbb2ef3e62f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339562927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.339562927
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.118386348
Short name T333
Test name
Test status
Simulation time 6769825435 ps
CPU time 112.8 seconds
Started Mar 12 12:54:13 PM PDT 24
Finished Mar 12 12:56:06 PM PDT 24
Peak memory 198260 kb
Host smart-cd2f6fdc-1ad4-4df7-ab1c-fde4776c871d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118386348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.118386348
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3021852140
Short name T582
Test name
Test status
Simulation time 451806424296 ps
CPU time 1881.56 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 01:25:41 PM PDT 24
Peak memory 198436 kb
Host smart-020d00b2-d312-4769-ab7f-1d1fdf5803bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3021852140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3021852140
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1662659886
Short name T445
Test name
Test status
Simulation time 24725847 ps
CPU time 0.59 seconds
Started Mar 12 12:54:15 PM PDT 24
Finished Mar 12 12:54:17 PM PDT 24
Peak memory 194236 kb
Host smart-5c2e71a2-f188-47c4-8abb-a8ebe1f1df39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662659886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1662659886
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2657275739
Short name T286
Test name
Test status
Simulation time 53863056 ps
CPU time 0.88 seconds
Started Mar 12 12:54:16 PM PDT 24
Finished Mar 12 12:54:18 PM PDT 24
Peak memory 197308 kb
Host smart-be1dc4b1-bc56-4e14-9028-9553a3c2daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657275739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2657275739
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3131079568
Short name T346
Test name
Test status
Simulation time 567969583 ps
CPU time 15.72 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:35 PM PDT 24
Peak memory 196904 kb
Host smart-600cef52-874e-40b7-b2be-8f3dfa4a6684
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131079568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3131079568
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4078715916
Short name T325
Test name
Test status
Simulation time 62732787 ps
CPU time 0.9 seconds
Started Mar 12 12:54:17 PM PDT 24
Finished Mar 12 12:54:18 PM PDT 24
Peak memory 196156 kb
Host smart-01596ef4-46cd-4f03-a24a-8554ae4ce8d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078715916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4078715916
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3223894973
Short name T390
Test name
Test status
Simulation time 105271470 ps
CPU time 0.92 seconds
Started Mar 12 12:54:14 PM PDT 24
Finished Mar 12 12:54:16 PM PDT 24
Peak memory 196716 kb
Host smart-d631be9d-c4e0-4e23-a418-7f3abfa5b682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223894973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3223894973
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1660464509
Short name T573
Test name
Test status
Simulation time 58354586 ps
CPU time 2.17 seconds
Started Mar 12 12:54:11 PM PDT 24
Finished Mar 12 12:54:13 PM PDT 24
Peak memory 198172 kb
Host smart-4839b759-bd80-42cf-b1cc-0b75aad4bdcf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660464509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1660464509
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1696442334
Short name T227
Test name
Test status
Simulation time 242640126 ps
CPU time 2.45 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 197272 kb
Host smart-aa61471f-5d75-4e62-9de4-06e82ea39d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696442334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1696442334
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.67438708
Short name T113
Test name
Test status
Simulation time 25583355 ps
CPU time 0.77 seconds
Started Mar 12 12:54:27 PM PDT 24
Finished Mar 12 12:54:28 PM PDT 24
Peak memory 195400 kb
Host smart-6439bff5-50b4-43b0-9787-e624eab3c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67438708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.67438708
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3916993134
Short name T708
Test name
Test status
Simulation time 74418320 ps
CPU time 1.01 seconds
Started Mar 12 12:54:25 PM PDT 24
Finished Mar 12 12:54:26 PM PDT 24
Peak memory 195952 kb
Host smart-709a7dd3-a1a3-4271-8208-3cd0f61cd2ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916993134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3916993134
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.926687272
Short name T176
Test name
Test status
Simulation time 257573517 ps
CPU time 2.97 seconds
Started Mar 12 12:54:34 PM PDT 24
Finished Mar 12 12:54:37 PM PDT 24
Peak memory 198084 kb
Host smart-014cdf8c-8bd3-4700-bd37-0cc0065df34d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926687272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.926687272
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.93903455
Short name T655
Test name
Test status
Simulation time 75620623 ps
CPU time 1.24 seconds
Started Mar 12 12:54:13 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 195940 kb
Host smart-15f72831-1423-4a46-a551-c82b7af5db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93903455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.93903455
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.333404778
Short name T345
Test name
Test status
Simulation time 162153567 ps
CPU time 0.89 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 195280 kb
Host smart-e98ac2de-76f7-45c4-97ba-6f68751db4d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333404778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.333404778
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.600527937
Short name T590
Test name
Test status
Simulation time 2899376075 ps
CPU time 34.18 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 198324 kb
Host smart-ba2f3b24-7191-46cc-9ca1-ff87cc5f1b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600527937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.600527937
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2129549702
Short name T431
Test name
Test status
Simulation time 81913688142 ps
CPU time 1632.21 seconds
Started Mar 12 12:54:08 PM PDT 24
Finished Mar 12 01:21:22 PM PDT 24
Peak memory 198452 kb
Host smart-a0a26b02-c419-4199-8d49-f4f5608cfbfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2129549702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2129549702
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1390927695
Short name T643
Test name
Test status
Simulation time 78833180 ps
CPU time 0.58 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 194268 kb
Host smart-92051eae-06db-409d-b86c-7d110e6f6acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390927695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1390927695
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1063864562
Short name T210
Test name
Test status
Simulation time 55310267 ps
CPU time 0.71 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 195936 kb
Host smart-a594c1d6-3d1d-4a7e-88a8-249fbe368527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063864562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1063864562
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.285859052
Short name T548
Test name
Test status
Simulation time 2250041515 ps
CPU time 15.77 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:39 PM PDT 24
Peak memory 195780 kb
Host smart-2d7a5103-20cc-4462-ace0-40f67e3461cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285859052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.285859052
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1692356862
Short name T339
Test name
Test status
Simulation time 220024896 ps
CPU time 0.93 seconds
Started Mar 12 12:54:26 PM PDT 24
Finished Mar 12 12:54:27 PM PDT 24
Peak memory 197268 kb
Host smart-c981f295-4ecc-4097-b6fb-d0617f08866b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692356862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1692356862
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.917872161
Short name T285
Test name
Test status
Simulation time 57350922 ps
CPU time 1.38 seconds
Started Mar 12 12:54:14 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 197124 kb
Host smart-2f948457-67c7-4ffe-9e5c-3cc37f8ef134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917872161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.917872161
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.389910032
Short name T314
Test name
Test status
Simulation time 78266938 ps
CPU time 2.86 seconds
Started Mar 12 12:54:13 PM PDT 24
Finished Mar 12 12:54:17 PM PDT 24
Peak memory 198052 kb
Host smart-8bd21b4e-7663-4f65-ab77-7848166a4850
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389910032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.389910032
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.367221639
Short name T348
Test name
Test status
Simulation time 146593066 ps
CPU time 1.61 seconds
Started Mar 12 12:54:38 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 196228 kb
Host smart-6d8be444-fad3-4fee-b9d7-3635739e171e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367221639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
367221639
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3672080130
Short name T650
Test name
Test status
Simulation time 260320860 ps
CPU time 0.76 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 196140 kb
Host smart-d8089d5f-7807-4132-ac9e-91dbd474bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672080130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3672080130
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1948918218
Short name T308
Test name
Test status
Simulation time 243167944 ps
CPU time 0.9 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 196124 kb
Host smart-74a85c2f-96f8-4dc2-930e-82cfc3ed5ac7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948918218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1948918218
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1977228893
Short name T10
Test name
Test status
Simulation time 84320424 ps
CPU time 1.3 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 198148 kb
Host smart-ec5777bc-9100-43dc-8f51-e781f934b3b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977228893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1977228893
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.760739891
Short name T501
Test name
Test status
Simulation time 102318553 ps
CPU time 0.98 seconds
Started Mar 12 12:54:12 PM PDT 24
Finished Mar 12 12:54:14 PM PDT 24
Peak memory 196052 kb
Host smart-80e42e0f-2fc8-4b27-a69b-ea027ab2d2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760739891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.760739891
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3138090688
Short name T707
Test name
Test status
Simulation time 29560715 ps
CPU time 0.93 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 196500 kb
Host smart-ee2d0d64-f996-46ac-9c4a-ca060c824532
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138090688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3138090688
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.961761490
Short name T244
Test name
Test status
Simulation time 8976133499 ps
CPU time 131.01 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:56:29 PM PDT 24
Peak memory 198316 kb
Host smart-30d928af-96c6-4ab7-b76d-6e67bd64c983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961761490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.961761490
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2743326540
Short name T617
Test name
Test status
Simulation time 14006167 ps
CPU time 0.57 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 194092 kb
Host smart-e8384e9a-d30a-47a4-b3ff-f4edb9db8710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743326540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2743326540
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.384643273
Short name T364
Test name
Test status
Simulation time 34732211 ps
CPU time 0.75 seconds
Started Mar 12 12:53:19 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 195240 kb
Host smart-1b987e3e-6e74-4f99-99db-9bd6d4b51c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384643273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.384643273
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3275217977
Short name T601
Test name
Test status
Simulation time 672975319 ps
CPU time 6.09 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196820 kb
Host smart-22e19178-72c6-4a24-9da5-6f941b570f70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275217977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3275217977
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3935229967
Short name T250
Test name
Test status
Simulation time 51809803 ps
CPU time 0.79 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 195908 kb
Host smart-f7f465a9-c829-4a93-99d0-5bd09c9c1dac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935229967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3935229967
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1609769706
Short name T207
Test name
Test status
Simulation time 113666330 ps
CPU time 0.77 seconds
Started Mar 12 12:52:54 PM PDT 24
Finished Mar 12 12:52:55 PM PDT 24
Peak memory 196296 kb
Host smart-661a834d-a0e3-476f-8a52-cd11ba9cbb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609769706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1609769706
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3970150248
Short name T309
Test name
Test status
Simulation time 196929126 ps
CPU time 2.98 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 196544 kb
Host smart-70c6eb69-a8a3-4295-aeee-681e5de75d37
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970150248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3970150248
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.608634136
Short name T640
Test name
Test status
Simulation time 172282532 ps
CPU time 3.11 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 196904 kb
Host smart-b1635496-0748-4a76-ba72-d530d27fe422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608634136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.608634136
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4190897661
Short name T616
Test name
Test status
Simulation time 153300080 ps
CPU time 0.98 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:10 PM PDT 24
Peak memory 196804 kb
Host smart-a10155aa-f0d0-46ad-86a1-4ca78e8fbb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190897661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4190897661
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.4152422988
Short name T536
Test name
Test status
Simulation time 31820462 ps
CPU time 0.65 seconds
Started Mar 12 12:52:56 PM PDT 24
Finished Mar 12 12:52:58 PM PDT 24
Peak memory 195036 kb
Host smart-07010723-fe5a-43e5-8e1d-d95a3d1fe099
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152422988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.4152422988
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3115054744
Short name T633
Test name
Test status
Simulation time 346991863 ps
CPU time 5.69 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 198116 kb
Host smart-c1ea9a13-b57a-4f07-9d55-72c580efb2a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115054744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3115054744
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2265632370
Short name T38
Test name
Test status
Simulation time 444506917 ps
CPU time 0.97 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 214916 kb
Host smart-d09cdf53-9da3-4337-aec2-eb23f3e77b7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265632370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2265632370
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.35057558
Short name T117
Test name
Test status
Simulation time 240275746 ps
CPU time 1.24 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 196568 kb
Host smart-f7177629-c2a9-4b3f-bfa8-5e703629094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35057558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.35057558
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.56196471
Short name T657
Test name
Test status
Simulation time 395916227 ps
CPU time 1.12 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 195604 kb
Host smart-a1154d1f-ab94-4b77-9317-40f79b55bae4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56196471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.56196471
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.556495065
Short name T368
Test name
Test status
Simulation time 241216621794 ps
CPU time 230.79 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:56:57 PM PDT 24
Peak memory 198100 kb
Host smart-80bb9917-d9c4-4dae-8b6b-5fb1af9e7cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556495065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.556495065
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3392571051
Short name T664
Test name
Test status
Simulation time 13770535 ps
CPU time 0.59 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 194056 kb
Host smart-5c5ce59d-6033-4eeb-b07e-c811d739d242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392571051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3392571051
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3450864034
Short name T171
Test name
Test status
Simulation time 35724950 ps
CPU time 0.84 seconds
Started Mar 12 12:54:22 PM PDT 24
Finished Mar 12 12:54:23 PM PDT 24
Peak memory 196104 kb
Host smart-625ae09d-7058-488f-9f09-5e6a1e0a4f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450864034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3450864034
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.717448364
Short name T133
Test name
Test status
Simulation time 900019872 ps
CPU time 25.87 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:46 PM PDT 24
Peak memory 196956 kb
Host smart-fa476dd2-4142-4045-9b3a-a5685e89add4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717448364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.717448364
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2829685213
Short name T141
Test name
Test status
Simulation time 132910153 ps
CPU time 0.81 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 195824 kb
Host smart-8711e74c-08e2-4582-8d15-3d9959e2ab29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829685213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2829685213
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3403245399
Short name T160
Test name
Test status
Simulation time 167270519 ps
CPU time 1.08 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:24 PM PDT 24
Peak memory 195708 kb
Host smart-03c8f1eb-6f2b-471a-a0f2-616a107d7551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403245399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3403245399
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3994157194
Short name T415
Test name
Test status
Simulation time 90888048 ps
CPU time 3.4 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 198172 kb
Host smart-f74b6eb6-3398-43a1-9bba-d156db0f7450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994157194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3994157194
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1762089606
Short name T634
Test name
Test status
Simulation time 130164209 ps
CPU time 1.52 seconds
Started Mar 12 12:54:29 PM PDT 24
Finished Mar 12 12:54:31 PM PDT 24
Peak memory 195984 kb
Host smart-c21f6841-ac38-4341-b9a1-b664a317610a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762089606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1762089606
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1672217433
Short name T132
Test name
Test status
Simulation time 624191926 ps
CPU time 1.22 seconds
Started Mar 12 12:54:13 PM PDT 24
Finished Mar 12 12:54:15 PM PDT 24
Peak memory 198132 kb
Host smart-3bde786d-d0ba-4c3c-848b-19a3365ab520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672217433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1672217433
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3771868596
Short name T215
Test name
Test status
Simulation time 233087668 ps
CPU time 1.28 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 197276 kb
Host smart-25100bdd-6c14-47a5-9133-834439ff7e09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771868596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3771868596
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1551153011
Short name T677
Test name
Test status
Simulation time 200738229 ps
CPU time 3.57 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:25 PM PDT 24
Peak memory 198144 kb
Host smart-8cebb44b-e043-47d7-b74b-2a3b68c7a935
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551153011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1551153011
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.507355987
Short name T329
Test name
Test status
Simulation time 126275812 ps
CPU time 1.03 seconds
Started Mar 12 12:54:14 PM PDT 24
Finished Mar 12 12:54:16 PM PDT 24
Peak memory 196588 kb
Host smart-98eee28f-ff1a-47af-89dd-41cf32552b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507355987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.507355987
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.321495051
Short name T372
Test name
Test status
Simulation time 207330671 ps
CPU time 1.06 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:25 PM PDT 24
Peak memory 195672 kb
Host smart-0fe0956e-5db7-471e-9ad6-9b2b59edafc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321495051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.321495051
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1239943148
Short name T170
Test name
Test status
Simulation time 10118048100 ps
CPU time 144.78 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:56:43 PM PDT 24
Peak memory 198328 kb
Host smart-6bacc48b-085b-4276-93d4-5c281a753fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239943148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1239943148
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3178267403
Short name T439
Test name
Test status
Simulation time 22069372 ps
CPU time 0.64 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 195024 kb
Host smart-56aa804a-7c2e-40c7-9f1b-f8cddac58d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178267403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3178267403
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1580578280
Short name T563
Test name
Test status
Simulation time 162759903 ps
CPU time 0.87 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 197280 kb
Host smart-7160a018-1753-409a-b2d7-bb06b41ef284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580578280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1580578280
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3968017040
Short name T604
Test name
Test status
Simulation time 928302160 ps
CPU time 26.87 seconds
Started Mar 12 12:54:15 PM PDT 24
Finished Mar 12 12:54:42 PM PDT 24
Peak memory 196408 kb
Host smart-c2a7ea7d-e068-4117-9887-d928d3d7cfb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968017040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3968017040
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2201265920
Short name T189
Test name
Test status
Simulation time 113182257 ps
CPU time 0.69 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:24 PM PDT 24
Peak memory 194740 kb
Host smart-217b2d84-78a3-4375-b32b-631d7d3d1116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201265920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2201265920
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1272260672
Short name T620
Test name
Test status
Simulation time 86133697 ps
CPU time 1.37 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 197296 kb
Host smart-d0af8e51-f73b-4185-88bb-e6e6261f0b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272260672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1272260672
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3290192315
Short name T96
Test name
Test status
Simulation time 302325103 ps
CPU time 3.69 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 197596 kb
Host smart-e62ac0f1-bf47-4d99-ba65-2f9c9311d385
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290192315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3290192315
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1862412258
Short name T313
Test name
Test status
Simulation time 114388100 ps
CPU time 3.33 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 197056 kb
Host smart-d525c55a-9bc9-4356-bcdb-93c1de9c8598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862412258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1862412258
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3555871668
Short name T486
Test name
Test status
Simulation time 142124605 ps
CPU time 0.93 seconds
Started Mar 12 12:54:14 PM PDT 24
Finished Mar 12 12:54:16 PM PDT 24
Peak memory 196040 kb
Host smart-5a7d904d-465c-4c44-a05b-ea5b7e836fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555871668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3555871668
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.700330079
Short name T683
Test name
Test status
Simulation time 13853942 ps
CPU time 0.61 seconds
Started Mar 12 12:54:26 PM PDT 24
Finished Mar 12 12:54:27 PM PDT 24
Peak memory 194424 kb
Host smart-4adfab89-e198-423d-a8be-500feb21011c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700330079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.700330079
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2166644085
Short name T5
Test name
Test status
Simulation time 438752240 ps
CPU time 2.54 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 198156 kb
Host smart-2febc0ae-c04c-45c4-9d2d-73aaf3687915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166644085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2166644085
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.267349920
Short name T554
Test name
Test status
Simulation time 114500855 ps
CPU time 1.16 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 195676 kb
Host smart-a83e6bfa-b7fe-47db-9414-35a1e83c7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267349920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.267349920
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3086574073
Short name T477
Test name
Test status
Simulation time 53859703 ps
CPU time 1.1 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 195932 kb
Host smart-c769b28f-a693-4bf1-a0fc-a54295fdca16
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086574073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3086574073
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1422789833
Short name T140
Test name
Test status
Simulation time 12593734162 ps
CPU time 158.01 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:57:11 PM PDT 24
Peak memory 198288 kb
Host smart-3fb8ff7c-9da7-4f24-852d-156bdce198dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422789833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1422789833
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3839096155
Short name T377
Test name
Test status
Simulation time 48988463 ps
CPU time 0.57 seconds
Started Mar 12 12:54:25 PM PDT 24
Finished Mar 12 12:54:26 PM PDT 24
Peak memory 194076 kb
Host smart-2d7aa94b-d3a2-4ba0-ae46-c7819c897168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839096155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3839096155
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3423460017
Short name T416
Test name
Test status
Simulation time 42384913 ps
CPU time 0.65 seconds
Started Mar 12 12:54:21 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 194088 kb
Host smart-585ee8f7-f8d3-4224-b217-cb2675cecf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423460017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3423460017
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4017091353
Short name T666
Test name
Test status
Simulation time 1229177568 ps
CPU time 7.75 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 198124 kb
Host smart-fd53cb23-8540-4c08-8c14-398867b7e757
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017091353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4017091353
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.4289134180
Short name T558
Test name
Test status
Simulation time 364521968 ps
CPU time 1 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 196420 kb
Host smart-a0af1385-9267-4f18-ae7d-325ad997f42b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289134180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.4289134180
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.939779033
Short name T327
Test name
Test status
Simulation time 28788018 ps
CPU time 0.86 seconds
Started Mar 12 12:54:29 PM PDT 24
Finished Mar 12 12:54:31 PM PDT 24
Peak memory 196716 kb
Host smart-ee9299eb-e914-4a3a-bbdb-990a96102836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939779033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.939779033
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2117230841
Short name T492
Test name
Test status
Simulation time 20090121 ps
CPU time 0.91 seconds
Started Mar 12 12:54:29 PM PDT 24
Finished Mar 12 12:54:31 PM PDT 24
Peak memory 196300 kb
Host smart-2bf99825-2554-4798-a272-19e0474303b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117230841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2117230841
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2266451073
Short name T606
Test name
Test status
Simulation time 130200699 ps
CPU time 2.31 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 197172 kb
Host smart-83923059-04c9-4cd3-a08e-2c53d6e2a16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266451073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2266451073
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3157402500
Short name T430
Test name
Test status
Simulation time 203658020 ps
CPU time 1.05 seconds
Started Mar 12 12:54:34 PM PDT 24
Finished Mar 12 12:54:35 PM PDT 24
Peak memory 195996 kb
Host smart-8a1eb1d8-fa70-457f-9d33-dba57c252256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157402500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3157402500
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1505392360
Short name T517
Test name
Test status
Simulation time 192872754 ps
CPU time 1.19 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:22 PM PDT 24
Peak memory 197132 kb
Host smart-66815ab5-6463-443b-8220-e98920d20a61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505392360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1505392360
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2848296494
Short name T191
Test name
Test status
Simulation time 103738407 ps
CPU time 4.19 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:23 PM PDT 24
Peak memory 198168 kb
Host smart-81525694-275e-40d8-9535-ffaa90123fa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848296494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2848296494
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3961460366
Short name T180
Test name
Test status
Simulation time 459591337 ps
CPU time 1.4 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:24 PM PDT 24
Peak memory 195660 kb
Host smart-c50b939b-d762-4268-9540-247f5a85c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961460366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3961460366
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.590991175
Short name T471
Test name
Test status
Simulation time 205189546 ps
CPU time 1.08 seconds
Started Mar 12 12:54:18 PM PDT 24
Finished Mar 12 12:54:19 PM PDT 24
Peak memory 195912 kb
Host smart-cdf701a7-bafb-4353-8174-cabfa9e7f9d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590991175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.590991175
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2965866692
Short name T709
Test name
Test status
Simulation time 24393498350 ps
CPU time 151.28 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:57:02 PM PDT 24
Peak memory 198240 kb
Host smart-c69192b3-1fff-4dd9-8ea9-017ab11bc68d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965866692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2965866692
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1511130627
Short name T229
Test name
Test status
Simulation time 97443401 ps
CPU time 0.57 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 194108 kb
Host smart-80041c89-dc3b-4bb0-9c62-f79e93ce8527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511130627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1511130627
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.964022930
Short name T183
Test name
Test status
Simulation time 118701355 ps
CPU time 0.57 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 193960 kb
Host smart-05d4885c-22a7-463b-ad8d-d0d474391d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964022930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.964022930
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3861595018
Short name T493
Test name
Test status
Simulation time 70222834 ps
CPU time 3.5 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 196504 kb
Host smart-11513cd4-f7e3-4e2d-a268-484dd0913479
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861595018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3861595018
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1912698975
Short name T564
Test name
Test status
Simulation time 154080035 ps
CPU time 1.1 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 196716 kb
Host smart-9c6b0ced-1a9b-4fec-9174-f580937e4189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912698975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1912698975
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1833508064
Short name T418
Test name
Test status
Simulation time 70565301 ps
CPU time 0.89 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 195636 kb
Host smart-3cacc28b-2c1b-47ed-9c24-6aee0bf575fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833508064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1833508064
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.205409083
Short name T272
Test name
Test status
Simulation time 171493293 ps
CPU time 1.78 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:34 PM PDT 24
Peak memory 197984 kb
Host smart-7dd79c2f-007d-47b8-9b6a-0b15ee889fb6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205409083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.205409083
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2839125845
Short name T25
Test name
Test status
Simulation time 2885798837 ps
CPU time 3.08 seconds
Started Mar 12 12:54:25 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 196220 kb
Host smart-0b9e00ac-eb51-4259-a5c3-8fe87f4ce5c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839125845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2839125845
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1252383087
Short name T665
Test name
Test status
Simulation time 481574565 ps
CPU time 1.23 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 196176 kb
Host smart-68db253c-fc1b-413b-87dc-e10612abb880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252383087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1252383087
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1419921575
Short name T373
Test name
Test status
Simulation time 153580979 ps
CPU time 1.38 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:34 PM PDT 24
Peak memory 197280 kb
Host smart-b41f704a-3fb0-4b58-94aa-d474fe499879
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419921575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1419921575
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.294324168
Short name T216
Test name
Test status
Simulation time 168922160 ps
CPU time 2.84 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:26 PM PDT 24
Peak memory 197812 kb
Host smart-fce7dd45-1273-43cd-a2e4-f72ce1a06a63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294324168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.294324168
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3498880962
Short name T182
Test name
Test status
Simulation time 56513196 ps
CPU time 0.72 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:24 PM PDT 24
Peak memory 195320 kb
Host smart-6bc30d04-07a1-4564-995b-230ee765cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498880962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3498880962
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2824373165
Short name T270
Test name
Test status
Simulation time 135412751 ps
CPU time 0.92 seconds
Started Mar 12 12:54:39 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 195204 kb
Host smart-766ed52f-bed3-4d58-827b-c53c782a52a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824373165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2824373165
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3430006896
Short name T545
Test name
Test status
Simulation time 7803662493 ps
CPU time 168.64 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:57:12 PM PDT 24
Peak memory 198308 kb
Host smart-02fdcd9a-b431-45cb-adb8-17abcdfc809d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430006896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3430006896
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3755726719
Short name T303
Test name
Test status
Simulation time 33097827 ps
CPU time 0.56 seconds
Started Mar 12 12:54:20 PM PDT 24
Finished Mar 12 12:54:21 PM PDT 24
Peak memory 194692 kb
Host smart-91b339d6-fd05-4d70-8a0a-c79feb72cd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755726719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3755726719
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2663919088
Short name T305
Test name
Test status
Simulation time 26721532 ps
CPU time 0.74 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 195288 kb
Host smart-03bcfd62-b2d5-4d97-9883-cf3f9d772ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663919088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2663919088
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3939732393
Short name T248
Test name
Test status
Simulation time 1803597944 ps
CPU time 25.38 seconds
Started Mar 12 12:54:26 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 197076 kb
Host smart-56e3e489-f742-478b-8a69-a5a46c3a6d24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939732393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3939732393
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.797075151
Short name T481
Test name
Test status
Simulation time 172283230 ps
CPU time 0.87 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 196832 kb
Host smart-e601ea8d-8966-4d9b-8dee-32b281b17d14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797075151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.797075151
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1177914023
Short name T361
Test name
Test status
Simulation time 49475705 ps
CPU time 0.97 seconds
Started Mar 12 12:54:37 PM PDT 24
Finished Mar 12 12:54:38 PM PDT 24
Peak memory 196572 kb
Host smart-24b38327-2d92-4273-8309-e537a981cd3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177914023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1177914023
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1346186303
Short name T116
Test name
Test status
Simulation time 323579454 ps
CPU time 2.75 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:38 PM PDT 24
Peak memory 197384 kb
Host smart-aa16f2b2-e76b-4236-9f78-bac6a13a687e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346186303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1346186303
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2456008544
Short name T637
Test name
Test status
Simulation time 95175230 ps
CPU time 1 seconds
Started Mar 12 12:54:26 PM PDT 24
Finished Mar 12 12:54:27 PM PDT 24
Peak memory 196008 kb
Host smart-1fb1e6ac-0068-4fbb-b0ab-6e2959b61b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456008544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2456008544
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.113519017
Short name T627
Test name
Test status
Simulation time 114878913 ps
CPU time 1.13 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:24 PM PDT 24
Peak memory 196980 kb
Host smart-c11d96d5-b6db-45f7-920c-ad1d5082e8b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113519017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.113519017
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3995978477
Short name T699
Test name
Test status
Simulation time 95433951 ps
CPU time 1.89 seconds
Started Mar 12 12:54:23 PM PDT 24
Finished Mar 12 12:54:25 PM PDT 24
Peak memory 198124 kb
Host smart-57c5dba5-97d2-4e1c-9b93-1c303c70c429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995978477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3995978477
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2177142967
Short name T242
Test name
Test status
Simulation time 43541402 ps
CPU time 1.14 seconds
Started Mar 12 12:54:34 PM PDT 24
Finished Mar 12 12:54:35 PM PDT 24
Peak memory 195956 kb
Host smart-4f871564-cd11-4f0e-b79d-bb6b7192c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177142967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2177142967
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.374195274
Short name T522
Test name
Test status
Simulation time 124221304 ps
CPU time 1.05 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:54:34 PM PDT 24
Peak memory 197360 kb
Host smart-683d2111-5920-435a-927d-9659c8fcb5a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374195274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.374195274
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3096021245
Short name T406
Test name
Test status
Simulation time 54271863330 ps
CPU time 219.74 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:58:22 PM PDT 24
Peak memory 198360 kb
Host smart-0c2cfe9a-d797-4fc2-8b68-2daee068e5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096021245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3096021245
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3098615754
Short name T695
Test name
Test status
Simulation time 16176937 ps
CPU time 0.55 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 193980 kb
Host smart-36630b24-8448-4baf-a5ff-4ff17a6878d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098615754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3098615754
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4059070444
Short name T421
Test name
Test status
Simulation time 595982033 ps
CPU time 0.87 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:42 PM PDT 24
Peak memory 196632 kb
Host smart-ccf8fd76-d176-4c20-bd0b-9c6e32bd7e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059070444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4059070444
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3928717105
Short name T449
Test name
Test status
Simulation time 3656423628 ps
CPU time 11.1 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 197168 kb
Host smart-c5c4d4ac-05af-4a37-bf69-37723b50d317
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928717105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3928717105
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3415127733
Short name T323
Test name
Test status
Simulation time 561227973 ps
CPU time 1.03 seconds
Started Mar 12 12:54:39 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 196796 kb
Host smart-58f07c8d-ed94-49f8-9a09-58de00cf0703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415127733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3415127733
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2563945480
Short name T319
Test name
Test status
Simulation time 243654391 ps
CPU time 1.24 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:42 PM PDT 24
Peak memory 196264 kb
Host smart-4d64fa5a-a086-410b-b3ce-7a76062568db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563945480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2563945480
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2007183018
Short name T231
Test name
Test status
Simulation time 95158488 ps
CPU time 1.14 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:46 PM PDT 24
Peak memory 197412 kb
Host smart-60cdf8d4-40b3-4fe1-99fa-27346d024c01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007183018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2007183018
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.578537231
Short name T684
Test name
Test status
Simulation time 144155330 ps
CPU time 3.04 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 198152 kb
Host smart-35ce9f89-5fcf-4dff-9637-e91eb5c4f077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578537231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
578537231
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2772305600
Short name T312
Test name
Test status
Simulation time 130971872 ps
CPU time 0.91 seconds
Started Mar 12 12:54:19 PM PDT 24
Finished Mar 12 12:54:20 PM PDT 24
Peak memory 196900 kb
Host smart-66d7507e-5e36-4567-a0d9-87d0d30c10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772305600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2772305600
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2331518762
Short name T586
Test name
Test status
Simulation time 24617915 ps
CPU time 1 seconds
Started Mar 12 12:54:34 PM PDT 24
Finished Mar 12 12:54:35 PM PDT 24
Peak memory 196800 kb
Host smart-b9dc7004-5037-4487-8d4e-d862e5d86c53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331518762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2331518762
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3033573920
Short name T531
Test name
Test status
Simulation time 106174938 ps
CPU time 1.88 seconds
Started Mar 12 12:54:37 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 198108 kb
Host smart-c3daca2b-f2c4-4ba2-9755-7d05846c6b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033573920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3033573920
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3210216346
Short name T473
Test name
Test status
Simulation time 82476055 ps
CPU time 1.29 seconds
Started Mar 12 12:54:33 PM PDT 24
Finished Mar 12 12:54:34 PM PDT 24
Peak memory 196760 kb
Host smart-de66d45f-7315-44e4-a3ff-59d7036447f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210216346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3210216346
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.503297554
Short name T158
Test name
Test status
Simulation time 22598863 ps
CPU time 0.81 seconds
Started Mar 12 12:54:27 PM PDT 24
Finished Mar 12 12:54:28 PM PDT 24
Peak memory 196092 kb
Host smart-9516328d-0b7d-4fe0-a12e-223c110d090b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503297554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.503297554
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2423423024
Short name T328
Test name
Test status
Simulation time 29061589986 ps
CPU time 75.94 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:56:02 PM PDT 24
Peak memory 198332 kb
Host smart-915fbd50-38f3-4e25-8e72-044ef89bb93e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423423024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2423423024
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2505645817
Short name T580
Test name
Test status
Simulation time 33453082 ps
CPU time 0.56 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 194104 kb
Host smart-b989a2a2-1d47-4615-91ed-310e2da00c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505645817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2505645817
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1295177443
Short name T243
Test name
Test status
Simulation time 57238375 ps
CPU time 0.63 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 194740 kb
Host smart-4c4ca3fd-e1e7-43ae-8567-2fbee22d4024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295177443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1295177443
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3011365593
Short name T350
Test name
Test status
Simulation time 614813993 ps
CPU time 17.39 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:55:04 PM PDT 24
Peak memory 196728 kb
Host smart-0d2bb7c9-516d-4b6e-9a16-465445dcc0fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011365593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3011365593
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3747163375
Short name T518
Test name
Test status
Simulation time 31267701 ps
CPU time 0.67 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 195340 kb
Host smart-94cd7a4b-8e28-4887-ad24-31af48256ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747163375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3747163375
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2632979874
Short name T31
Test name
Test status
Simulation time 58111205 ps
CPU time 0.94 seconds
Started Mar 12 12:54:40 PM PDT 24
Finished Mar 12 12:54:41 PM PDT 24
Peak memory 196772 kb
Host smart-01476ec8-2e8b-47e2-97df-c71069181ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632979874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2632979874
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2508062914
Short name T109
Test name
Test status
Simulation time 169494498 ps
CPU time 1.84 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 198184 kb
Host smart-b7216b75-eb95-42e7-b2da-deca7c96854a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508062914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2508062914
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3560681931
Short name T422
Test name
Test status
Simulation time 162887008 ps
CPU time 1.4 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 196084 kb
Host smart-f8eeed93-002f-42e4-be6a-ff2ee94327f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560681931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3560681931
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1103785751
Short name T680
Test name
Test status
Simulation time 232273441 ps
CPU time 1.22 seconds
Started Mar 12 12:54:39 PM PDT 24
Finished Mar 12 12:54:40 PM PDT 24
Peak memory 197004 kb
Host smart-a3f763c6-d8c4-4f83-b4d2-9cb7b4758d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103785751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1103785751
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2937202235
Short name T331
Test name
Test status
Simulation time 49825388 ps
CPU time 1.06 seconds
Started Mar 12 12:54:40 PM PDT 24
Finished Mar 12 12:54:41 PM PDT 24
Peak memory 195900 kb
Host smart-166e415c-788c-4512-addb-00a90c441a86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937202235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2937202235
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.344908996
Short name T336
Test name
Test status
Simulation time 1125217189 ps
CPU time 6.19 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 198080 kb
Host smart-3b1621bd-cefa-4da1-9422-a457d6028379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344908996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.344908996
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3289054096
Short name T11
Test name
Test status
Simulation time 54167972 ps
CPU time 0.97 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 195720 kb
Host smart-e860bc12-8cd9-44c0-84d9-50056017b419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289054096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3289054096
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1369151949
Short name T508
Test name
Test status
Simulation time 47559979 ps
CPU time 0.86 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:36 PM PDT 24
Peak memory 195852 kb
Host smart-b467966a-7e9a-4cc5-92f3-d19fa9c67a07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369151949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1369151949
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4254657298
Short name T53
Test name
Test status
Simulation time 31150380463 ps
CPU time 171.69 seconds
Started Mar 12 12:54:37 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 198288 kb
Host smart-2d93e0a3-17da-4bf0-a853-83f2d1dc9579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254657298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4254657298
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.789931220
Short name T570
Test name
Test status
Simulation time 274094328461 ps
CPU time 1498.66 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 01:19:27 PM PDT 24
Peak memory 198488 kb
Host smart-adf83939-19b9-4030-834f-372d6c3850c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=789931220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.789931220
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1919456714
Short name T453
Test name
Test status
Simulation time 23506803 ps
CPU time 0.54 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:44 PM PDT 24
Peak memory 192812 kb
Host smart-7ea46403-be20-499a-a749-b1e67f3d1b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919456714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1919456714
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1368414222
Short name T52
Test name
Test status
Simulation time 148039148 ps
CPU time 0.78 seconds
Started Mar 12 12:54:32 PM PDT 24
Finished Mar 12 12:54:33 PM PDT 24
Peak memory 195492 kb
Host smart-92c81a95-022a-4499-a71a-ead5a4bf1296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368414222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1368414222
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2405139239
Short name T534
Test name
Test status
Simulation time 789097304 ps
CPU time 13.86 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:55 PM PDT 24
Peak memory 198140 kb
Host smart-2ac7444f-ea47-431c-8262-419b22056086
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405139239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2405139239
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3734625966
Short name T585
Test name
Test status
Simulation time 36465304 ps
CPU time 0.76 seconds
Started Mar 12 12:54:28 PM PDT 24
Finished Mar 12 12:54:29 PM PDT 24
Peak memory 195980 kb
Host smart-c067362c-4499-4f12-9ca7-7725e695254d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734625966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3734625966
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3925349003
Short name T514
Test name
Test status
Simulation time 576521416 ps
CPU time 1.48 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 197048 kb
Host smart-65ef46cf-b286-4965-b517-e4d719840cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925349003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3925349003
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2922657283
Short name T460
Test name
Test status
Simulation time 21952421 ps
CPU time 1 seconds
Started Mar 12 12:54:35 PM PDT 24
Finished Mar 12 12:54:37 PM PDT 24
Peak memory 196032 kb
Host smart-d966f9de-6c11-4d6b-93fe-eb4a05cc521a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922657283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2922657283
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1034695406
Short name T186
Test name
Test status
Simulation time 379771884 ps
CPU time 1.88 seconds
Started Mar 12 12:54:36 PM PDT 24
Finished Mar 12 12:54:38 PM PDT 24
Peak memory 196100 kb
Host smart-4037e74b-8b71-4670-afea-c460c389fb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034695406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1034695406
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1960265454
Short name T181
Test name
Test status
Simulation time 70697983 ps
CPU time 0.83 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 196720 kb
Host smart-368eb98d-a22d-478e-9cc9-3cfdcae70ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960265454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1960265454
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3740339319
Short name T644
Test name
Test status
Simulation time 75537441 ps
CPU time 0.86 seconds
Started Mar 12 12:54:31 PM PDT 24
Finished Mar 12 12:54:32 PM PDT 24
Peak memory 196876 kb
Host smart-adaf7761-0e21-4393-9f32-7fa64473807e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740339319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3740339319
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.933624620
Short name T292
Test name
Test status
Simulation time 183196031 ps
CPU time 3.24 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 198152 kb
Host smart-2e301828-349c-4825-8f9b-84fff33760a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933624620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.933624620
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1638269826
Short name T200
Test name
Test status
Simulation time 126707364 ps
CPU time 1.09 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:44 PM PDT 24
Peak memory 196624 kb
Host smart-1bd15b08-c826-46a1-92e3-1c1394e5ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638269826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1638269826
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1401196881
Short name T461
Test name
Test status
Simulation time 504147175 ps
CPU time 1 seconds
Started Mar 12 12:54:39 PM PDT 24
Finished Mar 12 12:54:41 PM PDT 24
Peak memory 195920 kb
Host smart-fc50c3ea-23d4-4cfa-8721-bf7e5d1bacbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401196881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1401196881
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3953919673
Short name T9
Test name
Test status
Simulation time 6066392872 ps
CPU time 61.05 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:55:46 PM PDT 24
Peak memory 198224 kb
Host smart-a698f9bb-c872-4b5c-8ec4-99dbd31ac91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953919673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3953919673
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2684962290
Short name T598
Test name
Test status
Simulation time 278296393129 ps
CPU time 1811.85 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 01:24:56 PM PDT 24
Peak memory 198484 kb
Host smart-e749ed26-631a-49ce-81d5-0a93d31ccd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2684962290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2684962290
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3010249311
Short name T622
Test name
Test status
Simulation time 36497101 ps
CPU time 0.57 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:46 PM PDT 24
Peak memory 194100 kb
Host smart-4d1173bd-c906-4813-a108-376d1a4d1377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010249311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3010249311
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3298879542
Short name T23
Test name
Test status
Simulation time 20436433 ps
CPU time 0.7 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 194108 kb
Host smart-45d3809e-8fb2-4077-baa0-58eb32d1b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298879542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3298879542
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2761529112
Short name T138
Test name
Test status
Simulation time 1195648443 ps
CPU time 18.92 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:55:02 PM PDT 24
Peak memory 197048 kb
Host smart-432c8167-4e03-47ef-a4c4-a565c3dcddf6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761529112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2761529112
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3277188446
Short name T249
Test name
Test status
Simulation time 73435210 ps
CPU time 1.01 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 196608 kb
Host smart-0ded1156-619b-4a48-8d73-c8488aef3993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277188446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3277188446
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.4024744424
Short name T541
Test name
Test status
Simulation time 109540876 ps
CPU time 0.73 seconds
Started Mar 12 12:54:38 PM PDT 24
Finished Mar 12 12:54:39 PM PDT 24
Peak memory 195376 kb
Host smart-b50145fa-9737-45ac-b240-2cc5daccf51c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024744424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.4024744424
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3024009245
Short name T204
Test name
Test status
Simulation time 129605005 ps
CPU time 1.53 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:44 PM PDT 24
Peak memory 198204 kb
Host smart-837819e0-3914-4c60-924f-7e0c0b3638bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024009245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3024009245
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2669060048
Short name T656
Test name
Test status
Simulation time 151934349 ps
CPU time 1.01 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:43 PM PDT 24
Peak memory 196212 kb
Host smart-ca7e629f-cfcd-4285-a628-28ff75f81a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669060048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2669060048
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.84778813
Short name T527
Test name
Test status
Simulation time 44043082 ps
CPU time 1.12 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 196668 kb
Host smart-53a88124-b562-4c2c-b449-62c74de0f982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84778813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.84778813
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.767588434
Short name T211
Test name
Test status
Simulation time 78155565 ps
CPU time 0.97 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:42 PM PDT 24
Peak memory 196184 kb
Host smart-2d54a2b3-8d2f-49a3-87a1-ac02ca4f28f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767588434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.767588434
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4240908337
Short name T54
Test name
Test status
Simulation time 107407295 ps
CPU time 2.14 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:44 PM PDT 24
Peak memory 198144 kb
Host smart-fc3c7e2f-e23d-463c-9cf9-e6589189c4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240908337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4240908337
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3285533065
Short name T502
Test name
Test status
Simulation time 125626853 ps
CPU time 1.18 seconds
Started Mar 12 12:54:41 PM PDT 24
Finished Mar 12 12:54:42 PM PDT 24
Peak memory 195920 kb
Host smart-98cc879d-9dc9-43a3-a756-62cc7f0dd61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285533065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3285533065
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2137869778
Short name T521
Test name
Test status
Simulation time 181611230 ps
CPU time 0.92 seconds
Started Mar 12 12:54:42 PM PDT 24
Finished Mar 12 12:54:43 PM PDT 24
Peak memory 196276 kb
Host smart-ad1ffcf6-1d73-498d-8db5-044976b8d6b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137869778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2137869778
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.779215960
Short name T154
Test name
Test status
Simulation time 10504288568 ps
CPU time 140.78 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:57:11 PM PDT 24
Peak memory 198300 kb
Host smart-d2740dae-485a-44b7-bff3-6a88f416f2b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779215960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.779215960
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2332091626
Short name T553
Test name
Test status
Simulation time 60368306 ps
CPU time 0.54 seconds
Started Mar 12 12:54:43 PM PDT 24
Finished Mar 12 12:54:44 PM PDT 24
Peak memory 194052 kb
Host smart-10fbc8f3-4223-4888-8d0c-27f4b2b8dbc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332091626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2332091626
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.698282675
Short name T326
Test name
Test status
Simulation time 68638677 ps
CPU time 0.82 seconds
Started Mar 12 12:54:44 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 195332 kb
Host smart-d727da9d-7ece-4431-bc62-b02c51d754a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698282675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.698282675
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1429731962
Short name T235
Test name
Test status
Simulation time 1600526854 ps
CPU time 28 seconds
Started Mar 12 12:54:52 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 198164 kb
Host smart-b39f9cfc-f157-4a83-95c0-1644267495c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429731962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1429731962
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.440287800
Short name T529
Test name
Test status
Simulation time 19068706 ps
CPU time 0.64 seconds
Started Mar 12 12:54:45 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 194240 kb
Host smart-a19d3c96-81e5-412e-b1d2-75a8bf36c3df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440287800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.440287800
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2733982665
Short name T547
Test name
Test status
Simulation time 58805328 ps
CPU time 0.66 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 194496 kb
Host smart-9864b6b9-a264-400d-a8f1-641c10d7d119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733982665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2733982665
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.395115143
Short name T276
Test name
Test status
Simulation time 322557806 ps
CPU time 3.52 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 198188 kb
Host smart-a69aa464-6c54-4a7b-b0b4-951c5f0d2e8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395115143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.395115143
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3593148362
Short name T233
Test name
Test status
Simulation time 121211896 ps
CPU time 3.51 seconds
Started Mar 12 12:54:49 PM PDT 24
Finished Mar 12 12:54:53 PM PDT 24
Peak memory 197280 kb
Host smart-1094241b-4a9a-439f-acce-aa092aa0e1a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593148362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3593148362
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.778367020
Short name T653
Test name
Test status
Simulation time 35760315 ps
CPU time 0.84 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 196632 kb
Host smart-475b18ef-e77e-4482-bdf1-565b47b9082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778367020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.778367020
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.947253973
Short name T381
Test name
Test status
Simulation time 44375629 ps
CPU time 0.87 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 196128 kb
Host smart-edce20c1-0ddb-4693-9f69-a5f5818dc894
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947253973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.947253973
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.4024034361
Short name T413
Test name
Test status
Simulation time 169336738 ps
CPU time 2.1 seconds
Started Mar 12 12:54:47 PM PDT 24
Finished Mar 12 12:54:49 PM PDT 24
Peak memory 198108 kb
Host smart-0677fefb-e76e-4f44-8540-556ab8647a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024034361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.4024034361
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2246212786
Short name T441
Test name
Test status
Simulation time 168094645 ps
CPU time 1.44 seconds
Started Mar 12 12:54:46 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 196344 kb
Host smart-0f6f359d-2169-4a94-8386-93a0af1ff3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246212786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2246212786
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3349567902
Short name T190
Test name
Test status
Simulation time 44066414 ps
CPU time 1.3 seconds
Started Mar 12 12:54:48 PM PDT 24
Finished Mar 12 12:54:50 PM PDT 24
Peak memory 198088 kb
Host smart-d028712b-a108-4522-bac5-2b59d0464fdd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349567902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3349567902
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2912682645
Short name T393
Test name
Test status
Simulation time 23402851841 ps
CPU time 158.79 seconds
Started Mar 12 12:54:51 PM PDT 24
Finished Mar 12 12:57:30 PM PDT 24
Peak memory 198272 kb
Host smart-c9a736a6-7633-4351-adcc-061039288191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912682645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2912682645
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.431896320
Short name T419
Test name
Test status
Simulation time 13611494 ps
CPU time 0.56 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 194024 kb
Host smart-3cdf3329-e44e-41a4-ad65-ae5524a04e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431896320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.431896320
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.993921764
Short name T321
Test name
Test status
Simulation time 64226861 ps
CPU time 0.7 seconds
Started Mar 12 12:53:19 PM PDT 24
Finished Mar 12 12:53:20 PM PDT 24
Peak memory 195312 kb
Host smart-a8948f8b-448b-497a-b8d3-c5645801d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993921764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.993921764
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2594017314
Short name T134
Test name
Test status
Simulation time 2540089727 ps
CPU time 11.28 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:14 PM PDT 24
Peak memory 198280 kb
Host smart-32f047b9-f8bf-4671-96ec-24c91142f66c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594017314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2594017314
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3519197438
Short name T597
Test name
Test status
Simulation time 61362551 ps
CPU time 0.81 seconds
Started Mar 12 12:53:11 PM PDT 24
Finished Mar 12 12:53:13 PM PDT 24
Peak memory 196828 kb
Host smart-ad5dd6bc-f6ec-4f5a-8449-e21b4709031c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519197438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3519197438
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1922938101
Short name T464
Test name
Test status
Simulation time 32657437 ps
CPU time 0.68 seconds
Started Mar 12 12:53:18 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 194384 kb
Host smart-5be302c2-fd2e-4ad8-a01e-d84d8232cfbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922938101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1922938101
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2421960209
Short name T22
Test name
Test status
Simulation time 299969951 ps
CPU time 3.46 seconds
Started Mar 12 12:53:17 PM PDT 24
Finished Mar 12 12:53:20 PM PDT 24
Peak memory 198216 kb
Host smart-5b80ebda-be9a-4c36-8175-60600e493981
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421960209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2421960209
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1885644366
Short name T196
Test name
Test status
Simulation time 237896979 ps
CPU time 1.79 seconds
Started Mar 12 12:53:17 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 196332 kb
Host smart-d9cef4c9-7c78-4afa-b045-a3c5f39c0528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885644366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1885644366
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1605181552
Short name T30
Test name
Test status
Simulation time 19579972 ps
CPU time 0.69 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:10 PM PDT 24
Peak memory 194440 kb
Host smart-4bf5bd2a-87b5-497a-abab-405408a9eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605181552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1605181552
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.332096622
Short name T511
Test name
Test status
Simulation time 179890431 ps
CPU time 1 seconds
Started Mar 12 12:53:28 PM PDT 24
Finished Mar 12 12:53:29 PM PDT 24
Peak memory 196704 kb
Host smart-b6abcc7a-2557-47dd-ae27-5d415b9af207
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332096622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.332096622
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2516850762
Short name T299
Test name
Test status
Simulation time 2066576889 ps
CPU time 1.97 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 198016 kb
Host smart-77af011b-dfb1-40dd-a9ca-65300a5d16b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516850762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2516850762
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1089558853
Short name T491
Test name
Test status
Simulation time 327620638 ps
CPU time 0.82 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 196480 kb
Host smart-60001e1b-dcad-4b64-b1a9-8fa338aa834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089558853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1089558853
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2979749523
Short name T157
Test name
Test status
Simulation time 38689487 ps
CPU time 1.13 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 196712 kb
Host smart-af7ad8fc-2f46-4cd0-887d-7194bc63f994
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979749523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2979749523
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2781930108
Short name T4
Test name
Test status
Simulation time 18885405360 ps
CPU time 202.62 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:56:33 PM PDT 24
Peak memory 198348 kb
Host smart-fb951917-3fdf-4d0e-82ed-f3c0023b7517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781930108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2781930108
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2576394795
Short name T526
Test name
Test status
Simulation time 36631452 ps
CPU time 0.61 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 194124 kb
Host smart-7bb2e3e3-621a-492b-8232-a81be46ce18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576394795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2576394795
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2943194186
Short name T360
Test name
Test status
Simulation time 37954272 ps
CPU time 0.74 seconds
Started Mar 12 12:53:25 PM PDT 24
Finished Mar 12 12:53:26 PM PDT 24
Peak memory 195324 kb
Host smart-a72288d7-4665-4b37-b390-3026ff1f8889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943194186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2943194186
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2185828564
Short name T384
Test name
Test status
Simulation time 1392697274 ps
CPU time 9.92 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:15 PM PDT 24
Peak memory 197116 kb
Host smart-24c3fa92-10a1-4d40-a169-3c1a445b5ba8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185828564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2185828564
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.527381399
Short name T463
Test name
Test status
Simulation time 329356834 ps
CPU time 1.03 seconds
Started Mar 12 12:53:18 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 196532 kb
Host smart-ec787d99-a06e-4ca4-8885-29713baea4f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527381399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.527381399
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3253739728
Short name T318
Test name
Test status
Simulation time 166341888 ps
CPU time 1.16 seconds
Started Mar 12 12:53:13 PM PDT 24
Finished Mar 12 12:53:15 PM PDT 24
Peak memory 195936 kb
Host smart-873c078b-ec81-4299-af2d-6c15d5d099de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253739728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3253739728
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3951533396
Short name T700
Test name
Test status
Simulation time 232840933 ps
CPU time 1.74 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 196964 kb
Host smart-1f7da17f-2f1f-4327-94e1-d07ab22268ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951533396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3951533396
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.958696578
Short name T324
Test name
Test status
Simulation time 119430848 ps
CPU time 3.13 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 197232 kb
Host smart-262a594d-bc15-4f34-81f4-e8343d310502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958696578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.958696578
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1353087159
Short name T367
Test name
Test status
Simulation time 70005963 ps
CPU time 0.84 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 196724 kb
Host smart-8854c27a-493d-4643-9fd6-bf2535389351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353087159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1353087159
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3868374379
Short name T489
Test name
Test status
Simulation time 68718755 ps
CPU time 0.67 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 194232 kb
Host smart-33a29c80-5aea-4ba5-9792-09022269cb94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868374379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3868374379
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.626387975
Short name T490
Test name
Test status
Simulation time 870839015 ps
CPU time 5.13 seconds
Started Mar 12 12:53:10 PM PDT 24
Finished Mar 12 12:53:16 PM PDT 24
Peak memory 198192 kb
Host smart-823709a3-ec36-4858-80fe-92c858b3f13e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626387975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.626387975
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1343653211
Short name T146
Test name
Test status
Simulation time 130164698 ps
CPU time 1.04 seconds
Started Mar 12 12:53:10 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 195920 kb
Host smart-938876b0-cf87-43b3-8637-f554e93d38ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343653211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1343653211
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1913381999
Short name T15
Test name
Test status
Simulation time 428008063 ps
CPU time 1.29 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196460 kb
Host smart-3d7dcd67-e7bc-4da6-990f-2df8071e4f4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913381999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1913381999
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2095884568
Short name T414
Test name
Test status
Simulation time 24197810498 ps
CPU time 162.63 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:55:43 PM PDT 24
Peak memory 198320 kb
Host smart-24d15e38-c00c-41ee-b5b6-2684bb485475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095884568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2095884568
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.943326006
Short name T438
Test name
Test status
Simulation time 13094737 ps
CPU time 0.59 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 194060 kb
Host smart-9eec4698-67d4-45bc-9a08-8d1393cbd216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943326006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.943326006
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3590040163
Short name T378
Test name
Test status
Simulation time 28102333 ps
CPU time 0.72 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 194948 kb
Host smart-587f7fec-cb72-4171-ab1c-a6dad3fe816c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590040163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3590040163
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3636244757
Short name T98
Test name
Test status
Simulation time 281472811 ps
CPU time 14.06 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:17 PM PDT 24
Peak memory 197240 kb
Host smart-4347fd49-0a07-469e-a619-624dd6fcd7a6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636244757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3636244757
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1337129755
Short name T499
Test name
Test status
Simulation time 548612240 ps
CPU time 0.92 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 195940 kb
Host smart-8a996c81-304b-4b90-b061-679884f54965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337129755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1337129755
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.859895926
Short name T479
Test name
Test status
Simulation time 98609723 ps
CPU time 1.36 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 197168 kb
Host smart-e4469b2b-d4da-4c33-8710-8cf11ad3affb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859895926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.859895926
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3858524109
Short name T535
Test name
Test status
Simulation time 47682704 ps
CPU time 1.79 seconds
Started Mar 12 12:53:05 PM PDT 24
Finished Mar 12 12:53:07 PM PDT 24
Peak memory 198228 kb
Host smart-8bd966d9-fb2f-49b2-a3fa-b56e41194999
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858524109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3858524109
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.381610701
Short name T317
Test name
Test status
Simulation time 133443877 ps
CPU time 2.99 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 196668 kb
Host smart-a6ac04b5-ea29-48ec-a4f9-7f1e8fd7e400
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381610701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.381610701
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1574717549
Short name T476
Test name
Test status
Simulation time 79278792 ps
CPU time 1 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 196008 kb
Host smart-4ad37560-8971-4767-9084-d4510f5a6148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574717549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1574717549
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2398752881
Short name T316
Test name
Test status
Simulation time 102348427 ps
CPU time 1.05 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 195880 kb
Host smart-db010a59-bf82-4288-b3db-dfb0508c6760
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398752881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2398752881
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.55235692
Short name T681
Test name
Test status
Simulation time 892413329 ps
CPU time 3.12 seconds
Started Mar 12 12:53:14 PM PDT 24
Finished Mar 12 12:53:17 PM PDT 24
Peak memory 198132 kb
Host smart-fd9cfcc9-7a4e-4dff-bfa0-8506626892e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55235692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rando
m_long_reg_writes_reg_reads.55235692
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2556433176
Short name T255
Test name
Test status
Simulation time 108024463 ps
CPU time 1.11 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 195852 kb
Host smart-00b3e544-4324-4a5c-b3df-30dfd0a96d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556433176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2556433176
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1449343866
Short name T450
Test name
Test status
Simulation time 38767778 ps
CPU time 1.06 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:03 PM PDT 24
Peak memory 195696 kb
Host smart-8cd5d3aa-cfec-408b-8a94-08421fd75fae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449343866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1449343866
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1349152647
Short name T310
Test name
Test status
Simulation time 5104654635 ps
CPU time 140.16 seconds
Started Mar 12 12:53:21 PM PDT 24
Finished Mar 12 12:55:41 PM PDT 24
Peak memory 198216 kb
Host smart-47c418ef-1bb5-4294-bee6-d83990de7b2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349152647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1349152647
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3836806171
Short name T388
Test name
Test status
Simulation time 40794870 ps
CPU time 0.55 seconds
Started Mar 12 12:53:00 PM PDT 24
Finished Mar 12 12:53:01 PM PDT 24
Peak memory 194076 kb
Host smart-161c3cb0-8abe-4259-b844-a554987a2470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836806171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3836806171
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1861628811
Short name T641
Test name
Test status
Simulation time 77290548 ps
CPU time 0.89 seconds
Started Mar 12 12:53:03 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 195392 kb
Host smart-a6e2bffe-7bc4-4a1c-a44c-4ae825bccef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861628811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1861628811
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1899227996
Short name T429
Test name
Test status
Simulation time 861494201 ps
CPU time 23.75 seconds
Started Mar 12 12:53:13 PM PDT 24
Finished Mar 12 12:53:38 PM PDT 24
Peak memory 196888 kb
Host smart-354e8dfa-bd68-45c4-ad61-82d647332b6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899227996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1899227996
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1452054769
Short name T692
Test name
Test status
Simulation time 63443822 ps
CPU time 0.63 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:10 PM PDT 24
Peak memory 194556 kb
Host smart-783c96c8-66e1-438e-8f67-59ff4a27f9e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452054769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1452054769
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2439161152
Short name T400
Test name
Test status
Simulation time 181830915 ps
CPU time 1.26 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 198164 kb
Host smart-8153350b-43c3-4a91-b58d-902bc6f758f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439161152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2439161152
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2621014372
Short name T228
Test name
Test status
Simulation time 55647865 ps
CPU time 2.13 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 198148 kb
Host smart-40cc7e44-d861-475b-8645-4edaf3a7031c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621014372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2621014372
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3657039167
Short name T241
Test name
Test status
Simulation time 394918555 ps
CPU time 2.24 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 197312 kb
Host smart-86525a2c-93a2-4caa-9beb-a00dc18b51b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657039167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3657039167
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.578516503
Short name T574
Test name
Test status
Simulation time 36470416 ps
CPU time 0.93 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 196772 kb
Host smart-66179a4d-9a96-457a-a4c0-cd483e16c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578516503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.578516503
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3736453777
Short name T155
Test name
Test status
Simulation time 54055717 ps
CPU time 0.78 seconds
Started Mar 12 12:53:04 PM PDT 24
Finished Mar 12 12:53:05 PM PDT 24
Peak memory 196080 kb
Host smart-06dd1c76-eb83-4a9d-9d36-6b5853e94812
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736453777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3736453777
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3888286885
Short name T623
Test name
Test status
Simulation time 161847306 ps
CPU time 2.9 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 198120 kb
Host smart-95865003-902d-4094-a450-af968a09f8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888286885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3888286885
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3398470846
Short name T199
Test name
Test status
Simulation time 408512940 ps
CPU time 1.51 seconds
Started Mar 12 12:53:10 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 197004 kb
Host smart-f3482ed4-0410-45e8-b9c1-1d3187f7fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398470846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3398470846
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.544168789
Short name T197
Test name
Test status
Simulation time 517762623 ps
CPU time 1.17 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:02 PM PDT 24
Peak memory 196868 kb
Host smart-4867fabc-8306-405c-9fb1-38841ea4409c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544168789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.544168789
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3703308865
Short name T300
Test name
Test status
Simulation time 2290501328 ps
CPU time 31.73 seconds
Started Mar 12 12:53:20 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 198300 kb
Host smart-68541812-550f-4794-ad8d-b72bb32c53a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703308865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3703308865
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3036529808
Short name T33
Test name
Test status
Simulation time 229484422058 ps
CPU time 393.69 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 198500 kb
Host smart-109c5289-6565-413c-99f9-1608a1e258fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3036529808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3036529808
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1793597869
Short name T202
Test name
Test status
Simulation time 25712098 ps
CPU time 0.55 seconds
Started Mar 12 12:53:21 PM PDT 24
Finished Mar 12 12:53:22 PM PDT 24
Peak memory 194040 kb
Host smart-08c71ac4-7c64-4298-98c9-7bb5c4df4e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793597869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1793597869
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3197169389
Short name T546
Test name
Test status
Simulation time 24888933 ps
CPU time 0.8 seconds
Started Mar 12 12:53:08 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 195328 kb
Host smart-f3085261-6478-41b1-93e0-b203783c2461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197169389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3197169389
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3277519504
Short name T713
Test name
Test status
Simulation time 418277165 ps
CPU time 21.66 seconds
Started Mar 12 12:53:01 PM PDT 24
Finished Mar 12 12:53:23 PM PDT 24
Peak memory 196992 kb
Host smart-bde9495e-ff0f-4832-9ea3-0a5cebf763ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277519504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3277519504
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1929914813
Short name T714
Test name
Test status
Simulation time 76833727 ps
CPU time 0.92 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 197760 kb
Host smart-eaa10354-2b77-4e45-8d04-583a082f05f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929914813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1929914813
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4247310455
Short name T352
Test name
Test status
Simulation time 172163284 ps
CPU time 1.27 seconds
Started Mar 12 12:53:06 PM PDT 24
Finished Mar 12 12:53:08 PM PDT 24
Peak memory 198172 kb
Host smart-613f5f7d-5cb7-4630-97c3-1e827b10477c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247310455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4247310455
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1427346450
Short name T397
Test name
Test status
Simulation time 54567553 ps
CPU time 2.01 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 12:53:04 PM PDT 24
Peak memory 196420 kb
Host smart-e25a731f-f4d8-4709-8569-5c3f8d327938
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427346450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1427346450
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2692824531
Short name T347
Test name
Test status
Simulation time 101339611 ps
CPU time 1.66 seconds
Started Mar 12 12:53:23 PM PDT 24
Finished Mar 12 12:53:25 PM PDT 24
Peak memory 196128 kb
Host smart-0d9df35b-3b3e-468d-92df-d03d5d9fc40f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692824531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2692824531
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.974047490
Short name T192
Test name
Test status
Simulation time 44538862 ps
CPU time 0.79 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 196584 kb
Host smart-79e2a86e-779a-46f8-90e4-546fbd9ecdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974047490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.974047490
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.4029685093
Short name T648
Test name
Test status
Simulation time 53858424 ps
CPU time 0.64 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:11 PM PDT 24
Peak memory 194336 kb
Host smart-36625028-61a7-4e39-b6f2-e24abd66c904
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029685093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.4029685093
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2130794157
Short name T703
Test name
Test status
Simulation time 560732129 ps
CPU time 4.81 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:53:15 PM PDT 24
Peak memory 198040 kb
Host smart-6940de04-d512-49d0-bb3a-7759eec623ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130794157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2130794157
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1214862104
Short name T267
Test name
Test status
Simulation time 76874915 ps
CPU time 1.11 seconds
Started Mar 12 12:53:07 PM PDT 24
Finished Mar 12 12:53:09 PM PDT 24
Peak memory 196420 kb
Host smart-9e2fd5fd-7148-4c8d-ae6c-4d647e95f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214862104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1214862104
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4106926239
Short name T297
Test name
Test status
Simulation time 104282924 ps
CPU time 1.37 seconds
Started Mar 12 12:53:10 PM PDT 24
Finished Mar 12 12:53:12 PM PDT 24
Peak memory 196764 kb
Host smart-df4c5633-a054-4d55-8647-8c7f365bfffb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106926239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4106926239
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1130566641
Short name T148
Test name
Test status
Simulation time 6379781785 ps
CPU time 161.23 seconds
Started Mar 12 12:53:09 PM PDT 24
Finished Mar 12 12:55:51 PM PDT 24
Peak memory 198288 kb
Host smart-634b3c22-8881-4a54-907a-380d91cc5c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130566641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1130566641
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2982000160
Short name T32
Test name
Test status
Simulation time 29578612085 ps
CPU time 619.14 seconds
Started Mar 12 12:53:02 PM PDT 24
Finished Mar 12 01:03:21 PM PDT 24
Peak memory 198456 kb
Host smart-c6c9652f-8b31-4c3c-bab6-4ccf32a26cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2982000160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2982000160
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2926982437
Short name T918
Test name
Test status
Simulation time 47509012 ps
CPU time 1 seconds
Started Mar 12 12:29:39 PM PDT 24
Finished Mar 12 12:29:40 PM PDT 24
Peak memory 196392 kb
Host smart-a5adb69b-ce3b-47ae-9098-f00670103572
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2926982437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2926982437
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2029521737
Short name T881
Test name
Test status
Simulation time 40288477 ps
CPU time 0.99 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 197732 kb
Host smart-237a3122-72a3-4486-b23c-a5b3994a0d60
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029521737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2029521737
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1865831645
Short name T917
Test name
Test status
Simulation time 153748919 ps
CPU time 1.25 seconds
Started Mar 12 12:30:01 PM PDT 24
Finished Mar 12 12:30:08 PM PDT 24
Peak memory 196552 kb
Host smart-c94152cb-d4bb-4c54-b9d5-07e84c4c8199
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1865831645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1865831645
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1639802391
Short name T902
Test name
Test status
Simulation time 26816778 ps
CPU time 0.75 seconds
Started Mar 12 12:29:54 PM PDT 24
Finished Mar 12 12:29:55 PM PDT 24
Peak memory 195288 kb
Host smart-8b7dda1e-0087-4342-b214-32e144fc7e3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639802391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1639802391
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2561141549
Short name T863
Test name
Test status
Simulation time 136852826 ps
CPU time 1.2 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 195600 kb
Host smart-5e15a6e2-09bf-440f-91d2-5224de135efa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2561141549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2561141549
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.580936511
Short name T851
Test name
Test status
Simulation time 376785256 ps
CPU time 1.02 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 197724 kb
Host smart-3e767281-82c5-4d7c-9148-daef3a4fe68a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580936511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.580936511
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3315490962
Short name T931
Test name
Test status
Simulation time 352615716 ps
CPU time 1.33 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 197916 kb
Host smart-cea8a007-a08e-4a77-b05a-dde370d5633e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3315490962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3315490962
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3011131595
Short name T900
Test name
Test status
Simulation time 64040399 ps
CPU time 1.13 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:02 PM PDT 24
Peak memory 196660 kb
Host smart-e8b0fd24-1f36-4928-9b69-a65a2b3a3d76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011131595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3011131595
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3872485925
Short name T934
Test name
Test status
Simulation time 57390344 ps
CPU time 1.15 seconds
Started Mar 12 12:29:44 PM PDT 24
Finished Mar 12 12:29:46 PM PDT 24
Peak memory 196400 kb
Host smart-efe9f19e-45ac-4648-aa7b-ff98ceaf3b7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3872485925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3872485925
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813570962
Short name T857
Test name
Test status
Simulation time 44816442 ps
CPU time 0.92 seconds
Started Mar 12 12:29:46 PM PDT 24
Finished Mar 12 12:29:48 PM PDT 24
Peak memory 197220 kb
Host smart-3708377b-19d0-46c8-a648-fff7099e86ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813570962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1813570962
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.123298249
Short name T859
Test name
Test status
Simulation time 45124972 ps
CPU time 0.95 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 196460 kb
Host smart-c2ec9361-bd7e-4136-854b-b82d90752f81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=123298249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.123298249
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3554119094
Short name T879
Test name
Test status
Simulation time 60156783 ps
CPU time 1.01 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 196528 kb
Host smart-e85310a8-34fd-4554-8604-bd2e944c7419
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554119094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3554119094
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.382026826
Short name T850
Test name
Test status
Simulation time 172858731 ps
CPU time 1.22 seconds
Started Mar 12 12:29:49 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 198004 kb
Host smart-869311a5-e780-45dd-82f6-f15eb554763b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=382026826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.382026826
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1111962676
Short name T871
Test name
Test status
Simulation time 210128191 ps
CPU time 1.17 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 197476 kb
Host smart-42688cdc-c126-4c48-8fc5-38b6221c4a79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111962676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1111962676
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4014224478
Short name T908
Test name
Test status
Simulation time 171547781 ps
CPU time 0.99 seconds
Started Mar 12 12:29:46 PM PDT 24
Finished Mar 12 12:29:48 PM PDT 24
Peak memory 196516 kb
Host smart-6cbb18ea-4174-4504-8845-ef9c6936b0a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4014224478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4014224478
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1658890334
Short name T888
Test name
Test status
Simulation time 79476688 ps
CPU time 0.8 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 195216 kb
Host smart-0bc84f9d-b265-49da-8c3f-e1b753512689
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658890334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1658890334
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1635715470
Short name T914
Test name
Test status
Simulation time 94294823 ps
CPU time 1.44 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 197908 kb
Host smart-0766ae26-46a3-42b5-b67c-3ef649f5e872
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1635715470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1635715470
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.172288702
Short name T897
Test name
Test status
Simulation time 305385783 ps
CPU time 0.87 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:51 PM PDT 24
Peak memory 196088 kb
Host smart-1e5e6baf-76b1-422e-b7e2-4e07ab89206b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172288702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.172288702
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2455465321
Short name T913
Test name
Test status
Simulation time 155716380 ps
CPU time 1.59 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 196660 kb
Host smart-2be15611-5fc9-481f-8908-aee1a63163e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2455465321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2455465321
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151658853
Short name T922
Test name
Test status
Simulation time 174547247 ps
CPU time 1.25 seconds
Started Mar 12 12:29:43 PM PDT 24
Finished Mar 12 12:29:44 PM PDT 24
Peak memory 196828 kb
Host smart-64bee72e-5da4-47dc-86d9-2d13559cf94a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151658853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4151658853
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2527260046
Short name T847
Test name
Test status
Simulation time 31692308 ps
CPU time 1.03 seconds
Started Mar 12 12:29:47 PM PDT 24
Finished Mar 12 12:29:49 PM PDT 24
Peak memory 196432 kb
Host smart-480204d4-a2d6-44bb-8ef5-f17a584a28a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2527260046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2527260046
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4083472951
Short name T907
Test name
Test status
Simulation time 144404872 ps
CPU time 0.87 seconds
Started Mar 12 12:29:39 PM PDT 24
Finished Mar 12 12:29:40 PM PDT 24
Peak memory 197200 kb
Host smart-1d6307f8-a231-4098-93e7-a48fd11b9199
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083472951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4083472951
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4218724181
Short name T846
Test name
Test status
Simulation time 215521961 ps
CPU time 1.47 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:43 PM PDT 24
Peak memory 196776 kb
Host smart-70007e42-e766-48bd-b4da-153623eecbc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4218724181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4218724181
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2240017588
Short name T939
Test name
Test status
Simulation time 35197268 ps
CPU time 1 seconds
Started Mar 12 12:29:40 PM PDT 24
Finished Mar 12 12:29:42 PM PDT 24
Peak memory 195880 kb
Host smart-35a1557b-24af-4e90-9411-7034321324a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240017588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2240017588
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2970461254
Short name T901
Test name
Test status
Simulation time 165075837 ps
CPU time 1.28 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 196852 kb
Host smart-8e564b72-f6cf-4cea-9bb1-208d92bb902c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2970461254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2970461254
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2861733553
Short name T870
Test name
Test status
Simulation time 89919302 ps
CPU time 1.22 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196812 kb
Host smart-1bc3b186-9944-4c36-8d76-c5cbeb8cd9b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861733553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2861733553
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3616220358
Short name T843
Test name
Test status
Simulation time 180514043 ps
CPU time 1.42 seconds
Started Mar 12 12:29:47 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196456 kb
Host smart-82348654-b05a-4e0c-a67c-3d64d075d24d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3616220358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3616220358
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2514396486
Short name T915
Test name
Test status
Simulation time 101888582 ps
CPU time 1.18 seconds
Started Mar 12 12:29:47 PM PDT 24
Finished Mar 12 12:29:49 PM PDT 24
Peak memory 196464 kb
Host smart-86b8b830-00af-42dd-b943-df1b3bd0280a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514396486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2514396486
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4062561075
Short name T910
Test name
Test status
Simulation time 81218883 ps
CPU time 0.83 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 195288 kb
Host smart-97f72cf2-4cab-4e7a-932f-401b273e158c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4062561075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4062561075
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1322484093
Short name T937
Test name
Test status
Simulation time 38904830 ps
CPU time 1.09 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 195628 kb
Host smart-76c3c4a4-9d83-4fd1-b00b-67b083e20bcc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322484093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1322484093
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2220479814
Short name T866
Test name
Test status
Simulation time 236434594 ps
CPU time 1.15 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 196360 kb
Host smart-638ae0bf-033e-4de0-b5e8-172522a5888c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2220479814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2220479814
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1476910847
Short name T898
Test name
Test status
Simulation time 36730769 ps
CPU time 0.8 seconds
Started Mar 12 12:29:49 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 195860 kb
Host smart-bd83bad0-a63e-4c3c-92df-9485a54256fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476910847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1476910847
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1375426080
Short name T892
Test name
Test status
Simulation time 565060688 ps
CPU time 1.31 seconds
Started Mar 12 12:29:47 PM PDT 24
Finished Mar 12 12:29:48 PM PDT 24
Peak memory 197932 kb
Host smart-5c1e0419-f097-42af-bccb-45e7783c0845
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1375426080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1375426080
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474654841
Short name T862
Test name
Test status
Simulation time 797463959 ps
CPU time 1.29 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 195912 kb
Host smart-72cc3494-ed4e-4f94-953a-56d638c532aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474654841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.474654841
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.636317162
Short name T894
Test name
Test status
Simulation time 169600112 ps
CPU time 1.45 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196608 kb
Host smart-3b1c43d6-226b-42db-a6a5-fd37e2660091
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=636317162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.636317162
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544385810
Short name T882
Test name
Test status
Simulation time 68358132 ps
CPU time 1.35 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 196620 kb
Host smart-3cd44c20-82df-414e-b99f-067fe778b322
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544385810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1544385810
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1815825610
Short name T842
Test name
Test status
Simulation time 334018413 ps
CPU time 1 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 196324 kb
Host smart-523685e1-cfc6-4df0-8e5e-2e3b54ff9400
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1815825610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1815825610
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3137865611
Short name T923
Test name
Test status
Simulation time 40759346 ps
CPU time 0.91 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196048 kb
Host smart-013abea1-c409-4c21-ba99-53f0c53e886c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137865611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3137865611
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1394433403
Short name T845
Test name
Test status
Simulation time 33919628 ps
CPU time 1.02 seconds
Started Mar 12 12:29:49 PM PDT 24
Finished Mar 12 12:29:51 PM PDT 24
Peak memory 197936 kb
Host smart-9222622b-f280-4bc2-b030-e2cebfbbd418
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1394433403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1394433403
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.90686239
Short name T926
Test name
Test status
Simulation time 35898533 ps
CPU time 1.02 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 195880 kb
Host smart-e5dbea0e-1e24-4727-b449-05849d35d6f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90686239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.90686239
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1166755718
Short name T849
Test name
Test status
Simulation time 32016635 ps
CPU time 0.99 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196372 kb
Host smart-1029e8d4-b341-4eb3-84f9-d0fcf9941134
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1166755718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1166755718
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2329675047
Short name T889
Test name
Test status
Simulation time 849002450 ps
CPU time 1.13 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 197952 kb
Host smart-2c40fe27-f8e5-4b67-8dc6-a2d889f6752a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329675047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2329675047
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3063269533
Short name T891
Test name
Test status
Simulation time 243906912 ps
CPU time 1.29 seconds
Started Mar 12 12:30:01 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 196900 kb
Host smart-ba172f0a-c8e0-4327-be07-3acd3df1135a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3063269533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3063269533
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3278992070
Short name T872
Test name
Test status
Simulation time 109332987 ps
CPU time 1.13 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196704 kb
Host smart-80822b57-34c2-4f5a-a440-d93a199d7b93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278992070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3278992070
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.207905451
Short name T916
Test name
Test status
Simulation time 306519423 ps
CPU time 1.16 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 197436 kb
Host smart-a221ec1b-11b6-405d-b4f9-c612529c4fce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=207905451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.207905451
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223252838
Short name T885
Test name
Test status
Simulation time 120943970 ps
CPU time 0.85 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 195364 kb
Host smart-2a8cb825-4cee-4fa6-afbe-c2aed80b177f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223252838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2223252838
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1878567635
Short name T874
Test name
Test status
Simulation time 46097649 ps
CPU time 1.05 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 197148 kb
Host smart-17a8a22c-c45a-4628-91af-cceea8086198
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1878567635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1878567635
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1693104967
Short name T906
Test name
Test status
Simulation time 147088325 ps
CPU time 1.09 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 196392 kb
Host smart-9d1bf777-318d-4b78-b59b-7250db9b41dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693104967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1693104967
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.399357767
Short name T935
Test name
Test status
Simulation time 80093983 ps
CPU time 1.31 seconds
Started Mar 12 12:30:03 PM PDT 24
Finished Mar 12 12:30:05 PM PDT 24
Peak memory 196480 kb
Host smart-0d14040d-474a-4ded-bca1-bf9a268f140a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=399357767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.399357767
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.136781889
Short name T925
Test name
Test status
Simulation time 68809021 ps
CPU time 1.26 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:02 PM PDT 24
Peak memory 196684 kb
Host smart-84c865c1-75de-4966-bb89-4453bdc54218
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136781889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.136781889
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1927926496
Short name T930
Test name
Test status
Simulation time 155190840 ps
CPU time 1.46 seconds
Started Mar 12 12:30:06 PM PDT 24
Finished Mar 12 12:30:08 PM PDT 24
Peak memory 196716 kb
Host smart-107c08dd-82b7-48e9-bc05-159e4d9faf14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1927926496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1927926496
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986267948
Short name T927
Test name
Test status
Simulation time 59376632 ps
CPU time 0.96 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 196424 kb
Host smart-0eebccb5-5a34-412d-aee9-a7f06e086a52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986267948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2986267948
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3276621309
Short name T844
Test name
Test status
Simulation time 59807508 ps
CPU time 1.2 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 196356 kb
Host smart-68007d66-6034-4ac7-9654-000c2a2c91da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3276621309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3276621309
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3070003989
Short name T928
Test name
Test status
Simulation time 48493003 ps
CPU time 1.3 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 196428 kb
Host smart-3040ccc5-2688-4cda-9fd8-ccffd5366f76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070003989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3070003989
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3676511196
Short name T940
Test name
Test status
Simulation time 80620233 ps
CPU time 1.23 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196516 kb
Host smart-9c39e1ff-efc6-4ca9-b264-e279e978cf98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3676511196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3676511196
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410471800
Short name T864
Test name
Test status
Simulation time 108466704 ps
CPU time 1.24 seconds
Started Mar 12 12:29:50 PM PDT 24
Finished Mar 12 12:29:52 PM PDT 24
Peak memory 196492 kb
Host smart-817569c2-0b72-4b64-a820-a3f3cb0c270b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410471800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1410471800
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4188587915
Short name T880
Test name
Test status
Simulation time 360830780 ps
CPU time 0.95 seconds
Started Mar 12 12:29:54 PM PDT 24
Finished Mar 12 12:29:55 PM PDT 24
Peak memory 195580 kb
Host smart-40b0c162-cf31-414e-ac75-eeeb54c79af1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4188587915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4188587915
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373565308
Short name T858
Test name
Test status
Simulation time 77000322 ps
CPU time 1.29 seconds
Started Mar 12 12:29:54 PM PDT 24
Finished Mar 12 12:29:55 PM PDT 24
Peak memory 197960 kb
Host smart-7d29e038-cf90-4a17-92ed-25c4ee0e6f47
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373565308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3373565308
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2752532443
Short name T911
Test name
Test status
Simulation time 185392240 ps
CPU time 1.19 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 197344 kb
Host smart-f1857bda-408c-436a-9940-09696092898b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2752532443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2752532443
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501944573
Short name T899
Test name
Test status
Simulation time 400425893 ps
CPU time 1.29 seconds
Started Mar 12 12:30:10 PM PDT 24
Finished Mar 12 12:30:12 PM PDT 24
Peak memory 196908 kb
Host smart-eaedcef1-c4e2-44b5-95a1-fad39372c55e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501944573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2501944573
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1262006269
Short name T904
Test name
Test status
Simulation time 456587014 ps
CPU time 1.36 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 196580 kb
Host smart-12d22107-4101-4ee4-aaf4-a5dc08522407
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1262006269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1262006269
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1220622667
Short name T920
Test name
Test status
Simulation time 35639332 ps
CPU time 1.05 seconds
Started Mar 12 12:30:22 PM PDT 24
Finished Mar 12 12:30:24 PM PDT 24
Peak memory 196440 kb
Host smart-6dbfc3a5-7a17-44c1-9da1-08944487aeef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220622667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1220622667
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1208304133
Short name T877
Test name
Test status
Simulation time 48235867 ps
CPU time 0.83 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 195264 kb
Host smart-0e75c36e-5256-4f72-a26a-a8cc63a92629
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1208304133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1208304133
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.312451911
Short name T848
Test name
Test status
Simulation time 143357173 ps
CPU time 1.23 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 196796 kb
Host smart-f4059045-214a-4802-914f-1f91f10aa4b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312451911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.312451911
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2049926915
Short name T886
Test name
Test status
Simulation time 66947413 ps
CPU time 1.16 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 195904 kb
Host smart-8af17873-abab-47ab-9784-e18227a60f17
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2049926915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2049926915
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3259858010
Short name T860
Test name
Test status
Simulation time 46606268 ps
CPU time 1.18 seconds
Started Mar 12 12:29:52 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 196432 kb
Host smart-9cd40cd7-51e9-4d92-a00d-0ce57cd3ca22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259858010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3259858010
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3593417886
Short name T924
Test name
Test status
Simulation time 45014000 ps
CPU time 1.11 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 196544 kb
Host smart-963082b2-ef55-40d3-996f-82c71879953c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3593417886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3593417886
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3212624915
Short name T896
Test name
Test status
Simulation time 258651272 ps
CPU time 1.29 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:30:00 PM PDT 24
Peak memory 196512 kb
Host smart-9bcc91a9-55c5-4035-adb6-9025406677b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212624915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3212624915
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.166942123
Short name T903
Test name
Test status
Simulation time 285366037 ps
CPU time 1.44 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 196700 kb
Host smart-f3814b0a-b56b-48dc-ab61-2c78457be6ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=166942123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.166942123
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1429180453
Short name T867
Test name
Test status
Simulation time 763104732 ps
CPU time 1.3 seconds
Started Mar 12 12:29:48 PM PDT 24
Finished Mar 12 12:29:50 PM PDT 24
Peak memory 196724 kb
Host smart-de6b265d-ab17-4195-835f-ffa551c82c4a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429180453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1429180453
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1964683655
Short name T853
Test name
Test status
Simulation time 147831476 ps
CPU time 1.11 seconds
Started Mar 12 12:29:56 PM PDT 24
Finished Mar 12 12:29:58 PM PDT 24
Peak memory 196280 kb
Host smart-f9f17558-9ccd-4e68-b217-863fde447439
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1964683655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1964683655
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2857578891
Short name T921
Test name
Test status
Simulation time 175839540 ps
CPU time 1.4 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 197932 kb
Host smart-65e9640d-744c-44d2-a033-0026a42954b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857578891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2857578891
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3179931846
Short name T941
Test name
Test status
Simulation time 96988664 ps
CPU time 1.42 seconds
Started Mar 12 12:30:09 PM PDT 24
Finished Mar 12 12:30:11 PM PDT 24
Peak memory 196796 kb
Host smart-6313c187-f897-49cc-911e-ba98a8dc837f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3179931846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3179931846
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.516792330
Short name T933
Test name
Test status
Simulation time 254261944 ps
CPU time 1.21 seconds
Started Mar 12 12:30:15 PM PDT 24
Finished Mar 12 12:30:17 PM PDT 24
Peak memory 195936 kb
Host smart-531630f4-5108-4779-8d7c-b1d5668cf99e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516792330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.516792330
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3665800883
Short name T852
Test name
Test status
Simulation time 75729507 ps
CPU time 0.94 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 195468 kb
Host smart-5bbf445c-0f9b-49ad-ac2b-97c7a74d7697
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3665800883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3665800883
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206863393
Short name T854
Test name
Test status
Simulation time 166770767 ps
CPU time 0.92 seconds
Started Mar 12 12:29:58 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 195384 kb
Host smart-f3832a2c-0ecb-40a4-afcf-e35b44af09ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206863393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1206863393
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.29272742
Short name T887
Test name
Test status
Simulation time 128130775 ps
CPU time 1.18 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 196432 kb
Host smart-4144c34d-0c49-4d04-9129-eb7baf733b4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=29272742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.29272742
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1474004895
Short name T855
Test name
Test status
Simulation time 176600123 ps
CPU time 1.02 seconds
Started Mar 12 12:30:00 PM PDT 24
Finished Mar 12 12:30:01 PM PDT 24
Peak memory 195584 kb
Host smart-7951758e-d548-4c62-80cf-43f3e7544684
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474004895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1474004895
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2661514475
Short name T884
Test name
Test status
Simulation time 57769348 ps
CPU time 0.95 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 195872 kb
Host smart-9f035b66-9d7e-467a-b49d-8076a7e03184
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2661514475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2661514475
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4267270657
Short name T868
Test name
Test status
Simulation time 36359065 ps
CPU time 0.78 seconds
Started Mar 12 12:30:08 PM PDT 24
Finished Mar 12 12:30:08 PM PDT 24
Peak memory 195984 kb
Host smart-a5f497b1-b22f-48eb-8b63-97a8823661f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267270657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4267270657
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3721263478
Short name T909
Test name
Test status
Simulation time 70554137 ps
CPU time 1.3 seconds
Started Mar 12 12:30:16 PM PDT 24
Finished Mar 12 12:30:17 PM PDT 24
Peak memory 196588 kb
Host smart-6abe33ba-14a4-4d65-8653-1dda433f82d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3721263478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3721263478
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1692100840
Short name T861
Test name
Test status
Simulation time 76667773 ps
CPU time 0.91 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 196000 kb
Host smart-9c66130a-7ca3-42cd-b44b-499e05924224
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692100840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1692100840
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.269951859
Short name T929
Test name
Test status
Simulation time 136149554 ps
CPU time 0.87 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 195176 kb
Host smart-3e96f392-52a4-4819-a12d-728b833aadaa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=269951859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.269951859
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3622026787
Short name T878
Test name
Test status
Simulation time 153342830 ps
CPU time 1.19 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 195968 kb
Host smart-2cbcd6c0-c300-4e7e-aa8f-181ff442fe5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622026787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3622026787
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3126696186
Short name T932
Test name
Test status
Simulation time 204932881 ps
CPU time 1.08 seconds
Started Mar 12 12:30:14 PM PDT 24
Finished Mar 12 12:30:15 PM PDT 24
Peak memory 196492 kb
Host smart-4c7f9349-295f-4650-9058-639f2b43062e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3126696186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3126696186
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4261339554
Short name T938
Test name
Test status
Simulation time 37746664 ps
CPU time 1.1 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 197844 kb
Host smart-1a5ef991-9c41-4d13-8d67-c401986da8e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261339554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4261339554
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3564847873
Short name T895
Test name
Test status
Simulation time 206283748 ps
CPU time 1.06 seconds
Started Mar 12 12:29:57 PM PDT 24
Finished Mar 12 12:29:59 PM PDT 24
Peak memory 196608 kb
Host smart-1797966a-5073-47b0-8a33-ac04bf310c9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3564847873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3564847873
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1201532420
Short name T890
Test name
Test status
Simulation time 85687115 ps
CPU time 1.35 seconds
Started Mar 12 12:30:02 PM PDT 24
Finished Mar 12 12:30:04 PM PDT 24
Peak memory 196704 kb
Host smart-0ce9a704-4e27-4b2e-826e-bb821d1353e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201532420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1201532420
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2227424798
Short name T883
Test name
Test status
Simulation time 134742899 ps
CPU time 0.89 seconds
Started Mar 12 12:30:07 PM PDT 24
Finished Mar 12 12:30:08 PM PDT 24
Peak memory 195496 kb
Host smart-22947b7c-b968-4b87-83ef-aae90b011f0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2227424798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2227424798
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2878531707
Short name T893
Test name
Test status
Simulation time 65336504 ps
CPU time 1.26 seconds
Started Mar 12 12:30:13 PM PDT 24
Finished Mar 12 12:30:14 PM PDT 24
Peak memory 196464 kb
Host smart-9cbc5633-acb6-4994-ae0d-bb2899575530
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878531707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2878531707
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1982343632
Short name T865
Test name
Test status
Simulation time 133665709 ps
CPU time 1.21 seconds
Started Mar 12 12:29:53 PM PDT 24
Finished Mar 12 12:29:54 PM PDT 24
Peak memory 197580 kb
Host smart-66171cf3-8484-465d-8e4d-604e4931e7e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1982343632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1982343632
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844819308
Short name T856
Test name
Test status
Simulation time 46739732 ps
CPU time 1.05 seconds
Started Mar 12 12:29:54 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 197988 kb
Host smart-a2aa385f-9fdc-4bad-91e1-679634576e5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844819308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1844819308
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2729928562
Short name T869
Test name
Test status
Simulation time 182556732 ps
CPU time 0.96 seconds
Started Mar 12 12:29:42 PM PDT 24
Finished Mar 12 12:29:43 PM PDT 24
Peak memory 196492 kb
Host smart-9e89d329-fdb0-4f79-b017-30f6686a5187
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2729928562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2729928562
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49312568
Short name T876
Test name
Test status
Simulation time 129345029 ps
CPU time 1.11 seconds
Started Mar 12 12:29:43 PM PDT 24
Finished Mar 12 12:29:45 PM PDT 24
Peak memory 195900 kb
Host smart-0ac0ec65-a8d8-42ff-b7fc-7d60191fa8e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.49312568
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3223128129
Short name T905
Test name
Test status
Simulation time 83571973 ps
CPU time 1.28 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 198028 kb
Host smart-63d5d1fd-10fc-4237-88d2-35eda8379e70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3223128129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3223128129
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.253277521
Short name T919
Test name
Test status
Simulation time 78815556 ps
CPU time 1.26 seconds
Started Mar 12 12:30:01 PM PDT 24
Finished Mar 12 12:30:03 PM PDT 24
Peak memory 195768 kb
Host smart-74da6be9-fc2e-44e0-bf72-d3e9bdce65cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253277521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.253277521
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2051634571
Short name T912
Test name
Test status
Simulation time 53547647 ps
CPU time 1.38 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 196720 kb
Host smart-bc374eac-206a-446a-b370-168d2bb0b449
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2051634571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2051634571
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.974516179
Short name T873
Test name
Test status
Simulation time 120493822 ps
CPU time 1.01 seconds
Started Mar 12 12:29:54 PM PDT 24
Finished Mar 12 12:29:56 PM PDT 24
Peak memory 196512 kb
Host smart-6c511192-4b4e-4a09-ab88-14202143ad34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974516179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.974516179
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4047725756
Short name T936
Test name
Test status
Simulation time 29618681 ps
CPU time 0.91 seconds
Started Mar 12 12:29:51 PM PDT 24
Finished Mar 12 12:29:53 PM PDT 24
Peak memory 195252 kb
Host smart-69aaebd4-38dc-4963-99ae-0e8bd905d5a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4047725756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4047725756
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905450156
Short name T875
Test name
Test status
Simulation time 478341367 ps
CPU time 1.08 seconds
Started Mar 12 12:29:55 PM PDT 24
Finished Mar 12 12:29:57 PM PDT 24
Peak memory 195940 kb
Host smart-2cfba67b-d4b5-4007-bc01-31723d4083dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905450156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.905450156
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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