Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1822062 |
1 |
|
|
T32 |
80 |
|
T1 |
49 |
|
T11 |
218 |
| auto[1] |
1593905 |
1 |
|
|
T32 |
76 |
|
T1 |
33 |
|
T11 |
182 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2149699 |
1 |
|
|
T32 |
76 |
|
T1 |
54 |
|
T11 |
184 |
| auto[1] |
1266268 |
1 |
|
|
T32 |
80 |
|
T1 |
28 |
|
T11 |
216 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1184195 |
1 |
|
|
T32 |
37 |
|
T1 |
42 |
|
T11 |
104 |
| auto[0] |
auto[1] |
637867 |
1 |
|
|
T32 |
43 |
|
T1 |
7 |
|
T11 |
114 |
| auto[1] |
auto[0] |
965504 |
1 |
|
|
T32 |
39 |
|
T1 |
12 |
|
T11 |
80 |
| auto[1] |
auto[1] |
628401 |
1 |
|
|
T32 |
37 |
|
T1 |
21 |
|
T11 |
102 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1822843 |
1 |
|
|
T32 |
90 |
|
T1 |
49 |
|
T11 |
202 |
| auto[1] |
1593124 |
1 |
|
|
T32 |
66 |
|
T1 |
33 |
|
T11 |
198 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2147052 |
1 |
|
|
T32 |
68 |
|
T1 |
69 |
|
T11 |
213 |
| auto[1] |
1268915 |
1 |
|
|
T32 |
88 |
|
T1 |
13 |
|
T11 |
187 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1182864 |
1 |
|
|
T32 |
37 |
|
T1 |
46 |
|
T11 |
115 |
| auto[0] |
auto[1] |
639979 |
1 |
|
|
T32 |
53 |
|
T1 |
3 |
|
T11 |
87 |
| auto[1] |
auto[0] |
964188 |
1 |
|
|
T32 |
31 |
|
T1 |
23 |
|
T11 |
98 |
| auto[1] |
auto[1] |
628936 |
1 |
|
|
T32 |
35 |
|
T1 |
10 |
|
T11 |
100 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1816802 |
1 |
|
|
T32 |
86 |
|
T1 |
46 |
|
T11 |
204 |
| auto[1] |
1599165 |
1 |
|
|
T32 |
70 |
|
T1 |
36 |
|
T11 |
196 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2149274 |
1 |
|
|
T32 |
74 |
|
T1 |
62 |
|
T11 |
197 |
| auto[1] |
1266693 |
1 |
|
|
T32 |
82 |
|
T1 |
20 |
|
T11 |
203 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1180176 |
1 |
|
|
T32 |
47 |
|
T1 |
40 |
|
T11 |
97 |
| auto[0] |
auto[1] |
636626 |
1 |
|
|
T32 |
39 |
|
T1 |
6 |
|
T11 |
107 |
| auto[1] |
auto[0] |
969098 |
1 |
|
|
T32 |
27 |
|
T1 |
22 |
|
T11 |
100 |
| auto[1] |
auto[1] |
630067 |
1 |
|
|
T32 |
43 |
|
T1 |
14 |
|
T11 |
96 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1818590 |
1 |
|
|
T32 |
76 |
|
T1 |
53 |
|
T11 |
212 |
| auto[1] |
1597377 |
1 |
|
|
T32 |
80 |
|
T1 |
29 |
|
T11 |
188 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2147345 |
1 |
|
|
T32 |
92 |
|
T1 |
75 |
|
T11 |
194 |
| auto[1] |
1268622 |
1 |
|
|
T32 |
64 |
|
T1 |
7 |
|
T11 |
206 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1179976 |
1 |
|
|
T32 |
45 |
|
T1 |
53 |
|
T11 |
104 |
| auto[0] |
auto[1] |
638614 |
1 |
|
|
T32 |
31 |
|
T11 |
108 |
|
T12 |
87 |
| auto[1] |
auto[0] |
967369 |
1 |
|
|
T32 |
47 |
|
T1 |
22 |
|
T11 |
90 |
| auto[1] |
auto[1] |
630008 |
1 |
|
|
T32 |
33 |
|
T1 |
7 |
|
T11 |
98 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1822781 |
1 |
|
|
T32 |
84 |
|
T1 |
53 |
|
T11 |
190 |
| auto[1] |
1593186 |
1 |
|
|
T32 |
72 |
|
T1 |
29 |
|
T11 |
210 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2150639 |
1 |
|
|
T32 |
91 |
|
T1 |
78 |
|
T11 |
200 |
| auto[1] |
1265328 |
1 |
|
|
T32 |
65 |
|
T1 |
4 |
|
T11 |
200 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1184937 |
1 |
|
|
T32 |
46 |
|
T1 |
53 |
|
T11 |
99 |
| auto[0] |
auto[1] |
637844 |
1 |
|
|
T32 |
38 |
|
T11 |
91 |
|
T12 |
110 |
| auto[1] |
auto[0] |
965702 |
1 |
|
|
T32 |
45 |
|
T1 |
25 |
|
T11 |
101 |
| auto[1] |
auto[1] |
627484 |
1 |
|
|
T32 |
27 |
|
T1 |
4 |
|
T11 |
109 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821486 |
1 |
|
|
T32 |
66 |
|
T1 |
43 |
|
T11 |
196 |
| auto[1] |
1594481 |
1 |
|
|
T32 |
90 |
|
T1 |
39 |
|
T11 |
204 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2147745 |
1 |
|
|
T32 |
94 |
|
T1 |
77 |
|
T11 |
204 |
| auto[1] |
1268222 |
1 |
|
|
T32 |
62 |
|
T1 |
5 |
|
T11 |
196 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1182948 |
1 |
|
|
T32 |
43 |
|
T1 |
43 |
|
T11 |
96 |
| auto[0] |
auto[1] |
638538 |
1 |
|
|
T32 |
23 |
|
T11 |
100 |
|
T12 |
104 |
| auto[1] |
auto[0] |
964797 |
1 |
|
|
T32 |
51 |
|
T1 |
34 |
|
T11 |
108 |
| auto[1] |
auto[1] |
629684 |
1 |
|
|
T32 |
39 |
|
T1 |
5 |
|
T11 |
96 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1817580 |
1 |
|
|
T32 |
76 |
|
T1 |
59 |
|
T11 |
208 |
| auto[1] |
1598387 |
1 |
|
|
T32 |
80 |
|
T1 |
23 |
|
T11 |
192 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2146562 |
1 |
|
|
T32 |
83 |
|
T1 |
73 |
|
T11 |
213 |
| auto[1] |
1269405 |
1 |
|
|
T32 |
73 |
|
T1 |
9 |
|
T11 |
187 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1180106 |
1 |
|
|
T32 |
42 |
|
T1 |
54 |
|
T11 |
100 |
| auto[0] |
auto[1] |
637474 |
1 |
|
|
T32 |
34 |
|
T1 |
5 |
|
T11 |
108 |
| auto[1] |
auto[0] |
966456 |
1 |
|
|
T32 |
41 |
|
T1 |
19 |
|
T11 |
113 |
| auto[1] |
auto[1] |
631931 |
1 |
|
|
T32 |
39 |
|
T1 |
4 |
|
T11 |
79 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1827182 |
1 |
|
|
T32 |
80 |
|
T1 |
56 |
|
T11 |
176 |
| auto[1] |
1588785 |
1 |
|
|
T32 |
76 |
|
T1 |
26 |
|
T11 |
224 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2149757 |
1 |
|
|
T32 |
77 |
|
T1 |
70 |
|
T11 |
187 |
| auto[1] |
1266210 |
1 |
|
|
T32 |
79 |
|
T1 |
12 |
|
T11 |
213 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1187717 |
1 |
|
|
T32 |
34 |
|
T1 |
56 |
|
T11 |
78 |
| auto[0] |
auto[1] |
639465 |
1 |
|
|
T32 |
46 |
|
T11 |
98 |
|
T12 |
95 |
| auto[1] |
auto[0] |
962040 |
1 |
|
|
T32 |
43 |
|
T1 |
14 |
|
T11 |
109 |
| auto[1] |
auto[1] |
626745 |
1 |
|
|
T32 |
33 |
|
T1 |
12 |
|
T11 |
115 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1824708 |
1 |
|
|
T32 |
80 |
|
T1 |
52 |
|
T11 |
202 |
| auto[1] |
1591259 |
1 |
|
|
T32 |
76 |
|
T1 |
30 |
|
T11 |
198 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2153921 |
1 |
|
|
T32 |
65 |
|
T1 |
67 |
|
T11 |
178 |
| auto[1] |
1262046 |
1 |
|
|
T32 |
91 |
|
T1 |
15 |
|
T11 |
222 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1187695 |
1 |
|
|
T32 |
31 |
|
T1 |
50 |
|
T11 |
90 |
| auto[0] |
auto[1] |
637013 |
1 |
|
|
T32 |
49 |
|
T1 |
2 |
|
T11 |
112 |
| auto[1] |
auto[0] |
966226 |
1 |
|
|
T32 |
34 |
|
T1 |
17 |
|
T11 |
88 |
| auto[1] |
auto[1] |
625033 |
1 |
|
|
T32 |
42 |
|
T1 |
13 |
|
T11 |
110 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821311 |
1 |
|
|
T32 |
60 |
|
T1 |
48 |
|
T11 |
186 |
| auto[1] |
1594656 |
1 |
|
|
T32 |
96 |
|
T1 |
34 |
|
T11 |
214 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2155360 |
1 |
|
|
T32 |
82 |
|
T1 |
70 |
|
T11 |
177 |
| auto[1] |
1260607 |
1 |
|
|
T32 |
74 |
|
T1 |
12 |
|
T11 |
223 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1186009 |
1 |
|
|
T32 |
31 |
|
T1 |
42 |
|
T11 |
82 |
| auto[0] |
auto[1] |
635302 |
1 |
|
|
T32 |
29 |
|
T1 |
6 |
|
T11 |
104 |
| auto[1] |
auto[0] |
969351 |
1 |
|
|
T32 |
51 |
|
T1 |
28 |
|
T11 |
95 |
| auto[1] |
auto[1] |
625305 |
1 |
|
|
T32 |
45 |
|
T1 |
6 |
|
T11 |
119 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1822694 |
1 |
|
|
T32 |
66 |
|
T1 |
38 |
|
T11 |
206 |
| auto[1] |
1593273 |
1 |
|
|
T32 |
90 |
|
T1 |
44 |
|
T11 |
194 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2153165 |
1 |
|
|
T32 |
76 |
|
T1 |
73 |
|
T11 |
200 |
| auto[1] |
1262802 |
1 |
|
|
T32 |
80 |
|
T1 |
9 |
|
T11 |
200 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1185372 |
1 |
|
|
T32 |
36 |
|
T1 |
36 |
|
T11 |
97 |
| auto[0] |
auto[1] |
637322 |
1 |
|
|
T32 |
30 |
|
T1 |
2 |
|
T11 |
109 |
| auto[1] |
auto[0] |
967793 |
1 |
|
|
T32 |
40 |
|
T1 |
37 |
|
T11 |
103 |
| auto[1] |
auto[1] |
625480 |
1 |
|
|
T32 |
50 |
|
T1 |
7 |
|
T11 |
91 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1816528 |
1 |
|
|
T32 |
94 |
|
T1 |
68 |
|
T11 |
196 |
| auto[1] |
1599439 |
1 |
|
|
T32 |
62 |
|
T1 |
14 |
|
T11 |
204 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2150315 |
1 |
|
|
T32 |
80 |
|
T1 |
78 |
|
T11 |
189 |
| auto[1] |
1265652 |
1 |
|
|
T32 |
76 |
|
T1 |
4 |
|
T11 |
211 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1180834 |
1 |
|
|
T32 |
51 |
|
T1 |
66 |
|
T11 |
91 |
| auto[0] |
auto[1] |
635694 |
1 |
|
|
T32 |
43 |
|
T1 |
2 |
|
T11 |
105 |
| auto[1] |
auto[0] |
969481 |
1 |
|
|
T32 |
29 |
|
T1 |
12 |
|
T11 |
98 |
| auto[1] |
auto[1] |
629958 |
1 |
|
|
T32 |
33 |
|
T1 |
2 |
|
T11 |
106 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1820324 |
1 |
|
|
T32 |
82 |
|
T1 |
30 |
|
T11 |
210 |
| auto[1] |
1595643 |
1 |
|
|
T32 |
74 |
|
T1 |
52 |
|
T11 |
190 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2146958 |
1 |
|
|
T32 |
63 |
|
T1 |
64 |
|
T11 |
181 |
| auto[1] |
1269009 |
1 |
|
|
T32 |
93 |
|
T1 |
18 |
|
T11 |
219 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1181713 |
1 |
|
|
T32 |
29 |
|
T1 |
30 |
|
T11 |
93 |
| auto[0] |
auto[1] |
638611 |
1 |
|
|
T32 |
53 |
|
T11 |
117 |
|
T12 |
100 |
| auto[1] |
auto[0] |
965245 |
1 |
|
|
T32 |
34 |
|
T1 |
34 |
|
T11 |
88 |
| auto[1] |
auto[1] |
630398 |
1 |
|
|
T32 |
40 |
|
T1 |
18 |
|
T11 |
102 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1824422 |
1 |
|
|
T32 |
62 |
|
T1 |
51 |
|
T11 |
212 |
| auto[1] |
1591545 |
1 |
|
|
T32 |
94 |
|
T1 |
31 |
|
T11 |
188 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2152814 |
1 |
|
|
T32 |
81 |
|
T1 |
62 |
|
T11 |
195 |
| auto[1] |
1263153 |
1 |
|
|
T32 |
75 |
|
T1 |
20 |
|
T11 |
205 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1186754 |
1 |
|
|
T32 |
34 |
|
T1 |
37 |
|
T11 |
102 |
| auto[0] |
auto[1] |
637668 |
1 |
|
|
T32 |
28 |
|
T1 |
14 |
|
T11 |
110 |
| auto[1] |
auto[0] |
966060 |
1 |
|
|
T32 |
47 |
|
T1 |
25 |
|
T11 |
93 |
| auto[1] |
auto[1] |
625485 |
1 |
|
|
T32 |
47 |
|
T1 |
6 |
|
T11 |
95 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1818111 |
1 |
|
|
T32 |
80 |
|
T1 |
54 |
|
T11 |
196 |
| auto[1] |
1597856 |
1 |
|
|
T32 |
76 |
|
T1 |
28 |
|
T11 |
204 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2155005 |
1 |
|
|
T32 |
72 |
|
T1 |
71 |
|
T11 |
219 |
| auto[1] |
1260962 |
1 |
|
|
T32 |
84 |
|
T1 |
11 |
|
T11 |
181 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1185242 |
1 |
|
|
T32 |
39 |
|
T1 |
45 |
|
T11 |
114 |
| auto[0] |
auto[1] |
632869 |
1 |
|
|
T32 |
41 |
|
T1 |
9 |
|
T11 |
82 |
| auto[1] |
auto[0] |
969763 |
1 |
|
|
T32 |
33 |
|
T1 |
26 |
|
T11 |
105 |
| auto[1] |
auto[1] |
628093 |
1 |
|
|
T32 |
43 |
|
T1 |
2 |
|
T11 |
99 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1820852 |
1 |
|
|
T32 |
66 |
|
T1 |
58 |
|
T11 |
214 |
| auto[1] |
1595115 |
1 |
|
|
T32 |
90 |
|
T1 |
24 |
|
T11 |
186 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2151322 |
1 |
|
|
T32 |
60 |
|
T1 |
74 |
|
T11 |
201 |
| auto[1] |
1264645 |
1 |
|
|
T32 |
96 |
|
T1 |
8 |
|
T11 |
199 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1184168 |
1 |
|
|
T32 |
27 |
|
T1 |
58 |
|
T11 |
107 |
| auto[0] |
auto[1] |
636684 |
1 |
|
|
T32 |
39 |
|
T11 |
107 |
|
T12 |
97 |
| auto[1] |
auto[0] |
967154 |
1 |
|
|
T32 |
33 |
|
T1 |
16 |
|
T11 |
94 |
| auto[1] |
auto[1] |
627961 |
1 |
|
|
T32 |
57 |
|
T1 |
8 |
|
T11 |
92 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821828 |
1 |
|
|
T32 |
62 |
|
T1 |
62 |
|
T11 |
178 |
| auto[1] |
1594139 |
1 |
|
|
T32 |
94 |
|
T1 |
20 |
|
T11 |
222 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2152673 |
1 |
|
|
T32 |
78 |
|
T1 |
77 |
|
T11 |
205 |
| auto[1] |
1263294 |
1 |
|
|
T32 |
78 |
|
T1 |
5 |
|
T11 |
195 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1186566 |
1 |
|
|
T32 |
31 |
|
T1 |
57 |
|
T11 |
99 |
| auto[0] |
auto[1] |
635262 |
1 |
|
|
T32 |
31 |
|
T1 |
5 |
|
T11 |
79 |
| auto[1] |
auto[0] |
966107 |
1 |
|
|
T32 |
47 |
|
T1 |
20 |
|
T11 |
106 |
| auto[1] |
auto[1] |
628032 |
1 |
|
|
T32 |
47 |
|
T11 |
116 |
|
T12 |
95 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1818824 |
1 |
|
|
T32 |
74 |
|
T1 |
67 |
|
T11 |
198 |
| auto[1] |
1597143 |
1 |
|
|
T32 |
82 |
|
T1 |
15 |
|
T11 |
202 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2155439 |
1 |
|
|
T32 |
59 |
|
T1 |
80 |
|
T11 |
201 |
| auto[1] |
1260528 |
1 |
|
|
T32 |
97 |
|
T1 |
2 |
|
T11 |
199 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1184172 |
1 |
|
|
T32 |
23 |
|
T1 |
65 |
|
T11 |
94 |
| auto[0] |
auto[1] |
634652 |
1 |
|
|
T32 |
51 |
|
T1 |
2 |
|
T11 |
104 |
| auto[1] |
auto[0] |
971267 |
1 |
|
|
T32 |
36 |
|
T1 |
15 |
|
T11 |
107 |
| auto[1] |
auto[1] |
625876 |
1 |
|
|
T32 |
46 |
|
T11 |
95 |
|
T12 |
96 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1820653 |
1 |
|
|
T32 |
76 |
|
T1 |
65 |
|
T11 |
222 |
| auto[1] |
1595314 |
1 |
|
|
T32 |
80 |
|
T1 |
17 |
|
T11 |
178 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2156138 |
1 |
|
|
T32 |
67 |
|
T1 |
80 |
|
T11 |
183 |
| auto[1] |
1259829 |
1 |
|
|
T32 |
89 |
|
T1 |
2 |
|
T11 |
217 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1185036 |
1 |
|
|
T32 |
38 |
|
T1 |
63 |
|
T11 |
97 |
| auto[0] |
auto[1] |
635617 |
1 |
|
|
T32 |
38 |
|
T1 |
2 |
|
T11 |
125 |
| auto[1] |
auto[0] |
971102 |
1 |
|
|
T32 |
29 |
|
T1 |
17 |
|
T11 |
86 |
| auto[1] |
auto[1] |
624212 |
1 |
|
|
T32 |
51 |
|
T11 |
92 |
|
T12 |
108 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821751 |
1 |
|
|
T32 |
84 |
|
T1 |
60 |
|
T11 |
202 |
| auto[1] |
1594216 |
1 |
|
|
T32 |
72 |
|
T1 |
22 |
|
T11 |
198 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2155550 |
1 |
|
|
T32 |
83 |
|
T1 |
73 |
|
T11 |
178 |
| auto[1] |
1260417 |
1 |
|
|
T32 |
73 |
|
T1 |
9 |
|
T11 |
222 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1186256 |
1 |
|
|
T32 |
43 |
|
T1 |
57 |
|
T11 |
89 |
| auto[0] |
auto[1] |
635495 |
1 |
|
|
T32 |
41 |
|
T1 |
3 |
|
T11 |
113 |
| auto[1] |
auto[0] |
969294 |
1 |
|
|
T32 |
40 |
|
T1 |
16 |
|
T11 |
89 |
| auto[1] |
auto[1] |
624922 |
1 |
|
|
T32 |
32 |
|
T1 |
6 |
|
T11 |
109 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1816834 |
1 |
|
|
T32 |
82 |
|
T1 |
59 |
|
T11 |
186 |
| auto[1] |
1599133 |
1 |
|
|
T32 |
74 |
|
T1 |
23 |
|
T11 |
214 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2154077 |
1 |
|
|
T32 |
71 |
|
T1 |
77 |
|
T11 |
205 |
| auto[1] |
1261890 |
1 |
|
|
T32 |
85 |
|
T1 |
5 |
|
T11 |
195 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1182383 |
1 |
|
|
T32 |
40 |
|
T1 |
59 |
|
T11 |
97 |
| auto[0] |
auto[1] |
634451 |
1 |
|
|
T32 |
42 |
|
T11 |
89 |
|
T12 |
87 |
| auto[1] |
auto[0] |
971694 |
1 |
|
|
T32 |
31 |
|
T1 |
18 |
|
T11 |
108 |
| auto[1] |
auto[1] |
627439 |
1 |
|
|
T32 |
43 |
|
T1 |
5 |
|
T11 |
106 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1818374 |
1 |
|
|
T32 |
76 |
|
T1 |
59 |
|
T11 |
184 |
| auto[1] |
1597593 |
1 |
|
|
T32 |
80 |
|
T1 |
23 |
|
T11 |
216 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2154175 |
1 |
|
|
T32 |
57 |
|
T1 |
73 |
|
T11 |
203 |
| auto[1] |
1261792 |
1 |
|
|
T32 |
99 |
|
T1 |
9 |
|
T11 |
197 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1183992 |
1 |
|
|
T32 |
26 |
|
T1 |
57 |
|
T11 |
94 |
| auto[0] |
auto[1] |
634382 |
1 |
|
|
T32 |
50 |
|
T1 |
2 |
|
T11 |
90 |
| auto[1] |
auto[0] |
970183 |
1 |
|
|
T32 |
31 |
|
T1 |
16 |
|
T11 |
109 |
| auto[1] |
auto[1] |
627410 |
1 |
|
|
T32 |
49 |
|
T1 |
7 |
|
T11 |
107 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1819681 |
1 |
|
|
T32 |
78 |
|
T1 |
67 |
|
T11 |
188 |
| auto[1] |
1596286 |
1 |
|
|
T32 |
78 |
|
T1 |
15 |
|
T11 |
212 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2154911 |
1 |
|
|
T32 |
77 |
|
T1 |
78 |
|
T11 |
166 |
| auto[1] |
1261056 |
1 |
|
|
T32 |
79 |
|
T1 |
4 |
|
T11 |
234 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1185182 |
1 |
|
|
T32 |
38 |
|
T1 |
67 |
|
T11 |
74 |
| auto[0] |
auto[1] |
634499 |
1 |
|
|
T32 |
40 |
|
T11 |
114 |
|
T12 |
98 |
| auto[1] |
auto[0] |
969729 |
1 |
|
|
T32 |
39 |
|
T1 |
11 |
|
T11 |
92 |
| auto[1] |
auto[1] |
626557 |
1 |
|
|
T32 |
39 |
|
T1 |
4 |
|
T11 |
120 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821351 |
1 |
|
|
T32 |
82 |
|
T1 |
61 |
|
T11 |
188 |
| auto[1] |
1594616 |
1 |
|
|
T32 |
74 |
|
T1 |
21 |
|
T11 |
212 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2148753 |
1 |
|
|
T32 |
82 |
|
T1 |
80 |
|
T11 |
173 |
| auto[1] |
1267214 |
1 |
|
|
T32 |
74 |
|
T1 |
2 |
|
T11 |
227 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1183580 |
1 |
|
|
T32 |
39 |
|
T1 |
61 |
|
T11 |
81 |
| auto[0] |
auto[1] |
637771 |
1 |
|
|
T32 |
43 |
|
T11 |
107 |
|
T12 |
106 |
| auto[1] |
auto[0] |
965173 |
1 |
|
|
T32 |
43 |
|
T1 |
19 |
|
T11 |
92 |
| auto[1] |
auto[1] |
629443 |
1 |
|
|
T32 |
31 |
|
T1 |
2 |
|
T11 |
120 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1823508 |
1 |
|
|
T32 |
84 |
|
T1 |
45 |
|
T11 |
210 |
| auto[1] |
1592459 |
1 |
|
|
T32 |
72 |
|
T1 |
37 |
|
T11 |
190 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2157367 |
1 |
|
|
T32 |
79 |
|
T1 |
77 |
|
T11 |
225 |
| auto[1] |
1258600 |
1 |
|
|
T32 |
77 |
|
T1 |
5 |
|
T11 |
175 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1188201 |
1 |
|
|
T32 |
44 |
|
T1 |
45 |
|
T11 |
116 |
| auto[0] |
auto[1] |
635307 |
1 |
|
|
T32 |
40 |
|
T11 |
94 |
|
T12 |
90 |
| auto[1] |
auto[0] |
969166 |
1 |
|
|
T32 |
35 |
|
T1 |
32 |
|
T11 |
109 |
| auto[1] |
auto[1] |
623293 |
1 |
|
|
T32 |
37 |
|
T1 |
5 |
|
T11 |
81 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1821715 |
1 |
|
|
T32 |
70 |
|
T1 |
69 |
|
T11 |
184 |
| auto[1] |
1594252 |
1 |
|
|
T32 |
86 |
|
T1 |
13 |
|
T11 |
216 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2153682 |
1 |
|
|
T32 |
83 |
|
T1 |
74 |
|
T11 |
199 |
| auto[1] |
1262285 |
1 |
|
|
T32 |
73 |
|
T1 |
8 |
|
T11 |
201 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1186253 |
1 |
|
|
T32 |
39 |
|
T1 |
61 |
|
T11 |
102 |
| auto[0] |
auto[1] |
635462 |
1 |
|
|
T32 |
31 |
|
T1 |
8 |
|
T11 |
82 |
| auto[1] |
auto[0] |
967429 |
1 |
|
|
T32 |
44 |
|
T1 |
13 |
|
T11 |
97 |
| auto[1] |
auto[1] |
626823 |
1 |
|
|
T32 |
42 |
|
T11 |
119 |
|
T12 |
98 |
Summary for Variable cp_var1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
1817655 |
1 |
|
|
T32 |
82 |
|
T1 |
59 |
|
T11 |
188 |
| auto[1] |
1598312 |
1 |
|
|
T32 |
74 |
|
T1 |
23 |
|
T11 |
212 |
Summary for Variable cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
2147873 |
1 |
|
|
T32 |
74 |
|
T1 |
74 |
|
T11 |
201 |
| auto[1] |
1268094 |
1 |
|
|
T32 |
82 |
|
T1 |
8 |
|
T11 |
199 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
| cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
1178420 |
1 |
|
|
T32 |
42 |
|
T1 |
59 |
|
T11 |
93 |
| auto[0] |
auto[1] |
639235 |
1 |
|
|
T32 |
40 |
|
T11 |
95 |
|
T12 |
94 |
| auto[1] |
auto[0] |
969453 |
1 |
|
|
T32 |
32 |
|
T1 |
15 |
|
T11 |
108 |
| auto[1] |
auto[1] |
628859 |
1 |
|
|
T32 |
42 |
|
T1 |
8 |
|
T11 |
104 |