Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3740833	1			T32	1		T1	43		T11	1
all_pins[1]	3740833	1			T32	1		T1	43		T11	1
all_pins[2]	3740833	1			T32	1		T1	43		T11	1
all_pins[3]	3740833	1			T32	1		T1	43		T11	1
all_pins[4]	3740833	1			T32	1		T1	43		T11	1
all_pins[5]	3740833	1			T32	1		T1	43		T11	1
all_pins[6]	3740833	1			T32	1		T1	43		T11	1
all_pins[7]	3740833	1			T32	1		T1	43		T11	1
all_pins[8]	3740833	1			T32	1		T1	43		T11	1
all_pins[9]	3740833	1			T32	1		T1	43		T11	1
all_pins[10]	3740833	1			T32	1		T1	43		T11	1
all_pins[11]	3740833	1			T32	1		T1	43		T11	1
all_pins[12]	3740833	1			T32	1		T1	43		T11	1
all_pins[13]	3740833	1			T32	1		T1	43		T11	1
all_pins[14]	3740833	1			T32	1		T1	43		T11	1
all_pins[15]	3740833	1			T32	1		T1	43		T11	1
all_pins[16]	3740833	1			T32	1		T1	43		T11	1
all_pins[17]	3740833	1			T32	1		T1	43		T11	1
all_pins[18]	3740833	1			T32	1		T1	43		T11	1
all_pins[19]	3740833	1			T32	1		T1	43		T11	1
all_pins[20]	3740833	1			T32	1		T1	43		T11	1
all_pins[21]	3740833	1			T32	1		T1	43		T11	1
all_pins[22]	3740833	1			T32	1		T1	43		T11	1
all_pins[23]	3740833	1			T32	1		T1	43		T11	1
all_pins[24]	3740833	1			T32	1		T1	43		T11	1
all_pins[25]	3740833	1			T32	1		T1	43		T11	1
all_pins[26]	3740833	1			T32	1		T1	43		T11	1
all_pins[27]	3740833	1			T32	1		T1	43		T11	1
all_pins[28]	3740833	1			T32	1		T1	43		T11	1
all_pins[29]	3740833	1			T32	1		T1	43		T11	1
all_pins[30]	3740833	1			T32	1		T1	43		T11	1
all_pins[31]	3740833	1			T32	1		T1	43		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	74385747	1			T32	32		T1	1134		T11	32
values[0x1]	45320909	1			T1	242		T14	215		T16	214888
transitions[0x0=>0x1]	27167888	1			T1	159		T14	159		T16	129880
transitions[0x1=>0x0]	27167729	1			T1	159		T14	158		T16	129879

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2323815	1			T32	1		T1	41		T11	1
all_pins[0]	values[0x1]	1417018	1			T1	2		T14	6		T16	6798
all_pins[0]	transitions[0x0=>0x1]	877748	1			T1	1		T14	4		T16	4220
all_pins[0]	transitions[0x1=>0x0]	878270	1			T1	5		T14	8		T16	4149
all_pins[1]	values[0x0]	2329403	1			T32	1		T1	25		T11	1
all_pins[1]	values[0x1]	1411430	1			T1	18		T14	4		T16	6300
all_pins[1]	transitions[0x0=>0x1]	847631	1			T1	16		T14	4		T16	3840
all_pins[1]	transitions[0x1=>0x0]	853219	1			T14	6		T16	4338		T112	89
all_pins[2]	values[0x0]	2334332	1			T32	1		T1	38		T11	1
all_pins[2]	values[0x1]	1406501	1			T1	5		T14	6		T16	7016
all_pins[2]	transitions[0x0=>0x1]	844225	1			T1	1		T14	6		T16	4364
all_pins[2]	transitions[0x1=>0x0]	849154	1			T1	14		T14	4		T16	3648
all_pins[3]	values[0x0]	2321509	1			T32	1		T1	27		T11	1
all_pins[3]	values[0x1]	1419324	1			T1	16		T16	6962		T112	169
all_pins[3]	transitions[0x0=>0x1]	854619	1			T1	14		T16	3991		T112	109
all_pins[3]	transitions[0x1=>0x0]	841796	1			T1	3		T14	6		T16	4045
all_pins[4]	values[0x0]	2326600	1			T32	1		T1	43		T11	1
all_pins[4]	values[0x1]	1414233	1			T14	12		T16	6663		T112	197
all_pins[4]	transitions[0x0=>0x1]	844159	1			T14	12		T16	4057		T112	96
all_pins[4]	transitions[0x1=>0x0]	849250	1			T1	16		T16	4356		T112	68
all_pins[5]	values[0x0]	2330804	1			T32	1		T1	40		T11	1
all_pins[5]	values[0x1]	1410029	1			T1	3		T14	8		T16	6750
all_pins[5]	transitions[0x0=>0x1]	845592	1			T1	3		T14	5		T16	4297
all_pins[5]	transitions[0x1=>0x0]	849796	1			T14	9		T16	4210		T112	113
all_pins[6]	values[0x0]	2320105	1			T32	1		T1	36		T11	1
all_pins[6]	values[0x1]	1420728	1			T1	7		T14	5		T16	6853
all_pins[6]	transitions[0x0=>0x1]	853205	1			T1	5		T14	2		T16	4195
all_pins[6]	transitions[0x1=>0x0]	842506	1			T1	1		T14	5		T16	4092
all_pins[7]	values[0x0]	2320724	1			T32	1		T1	33		T11	1
all_pins[7]	values[0x1]	1420109	1			T1	10		T14	10		T16	6549
all_pins[7]	transitions[0x0=>0x1]	846538	1			T1	3		T14	7		T16	3881
all_pins[7]	transitions[0x1=>0x0]	847157	1			T14	2		T16	4185		T112	71
all_pins[8]	values[0x0]	2321858	1			T32	1		T1	33		T11	1
all_pins[8]	values[0x1]	1418975	1			T1	10		T14	9		T16	6694
all_pins[8]	transitions[0x0=>0x1]	848406	1			T1	6		T14	5		T16	4356
all_pins[8]	transitions[0x1=>0x0]	849540	1			T1	6		T14	6		T16	4211
all_pins[9]	values[0x0]	2319788	1			T32	1		T1	37		T11	1
all_pins[9]	values[0x1]	1421045	1			T1	6		T14	2		T16	6636
all_pins[9]	transitions[0x0=>0x1]	851941	1			T1	5		T14	2		T16	3908
all_pins[9]	transitions[0x1=>0x0]	849871	1			T1	9		T14	9		T16	3966
all_pins[10]	values[0x0]	2325659	1			T32	1		T1	34		T11	1
all_pins[10]	values[0x1]	1415174	1			T1	9		T14	5		T16	6736
all_pins[10]	transitions[0x0=>0x1]	849437	1			T1	9		T14	4		T16	4127
all_pins[10]	transitions[0x1=>0x0]	855308	1			T1	6		T14	1		T16	4027
all_pins[11]	values[0x0]	2321309	1			T32	1		T1	36		T11	1
all_pins[11]	values[0x1]	1419524	1			T1	7		T14	5		T16	6492
all_pins[11]	transitions[0x0=>0x1]	851328	1			T1	3		T14	3		T16	4039
all_pins[11]	transitions[0x1=>0x0]	846978	1			T1	5		T14	3		T16	4283
all_pins[12]	values[0x0]	2325855	1			T32	1		T1	38		T11	1
all_pins[12]	values[0x1]	1414978	1			T1	5		T14	15		T16	6536
all_pins[12]	transitions[0x0=>0x1]	844695	1			T1	3		T14	15		T16	3966
all_pins[12]	transitions[0x1=>0x0]	849241	1			T1	5		T14	5		T16	3922
all_pins[13]	values[0x0]	2322721	1			T32	1		T1	36		T11	1
all_pins[13]	values[0x1]	1418112	1			T1	7		T16	7015		T112	191
all_pins[13]	transitions[0x0=>0x1]	850090	1			T1	7		T16	4416		T112	107
all_pins[13]	transitions[0x1=>0x0]	846956	1			T1	5		T14	15		T16	3937
all_pins[14]	values[0x0]	2321309	1			T32	1		T1	38		T11	1
all_pins[14]	values[0x1]	1419524	1			T1	5		T14	1		T16	6625
all_pins[14]	transitions[0x0=>0x1]	846707	1			T1	2		T14	1		T16	3799
all_pins[14]	transitions[0x1=>0x0]	845295	1			T1	4		T16	4189		T112	133
all_pins[15]	values[0x0]	2319847	1			T32	1		T1	43		T11	1
all_pins[15]	values[0x1]	1420986	1			T14	2		T16	6497		T112	95
all_pins[15]	transitions[0x0=>0x1]	847738	1			T14	2		T16	4007		T112	53
all_pins[15]	transitions[0x1=>0x0]	846276	1			T1	5		T14	1		T16	4135
all_pins[16]	values[0x0]	2327842	1			T32	1		T1	38		T11	1
all_pins[16]	values[0x1]	1412991	1			T1	5		T14	7		T16	6409
all_pins[16]	transitions[0x0=>0x1]	845568	1			T1	5		T14	7		T16	3841
all_pins[16]	transitions[0x1=>0x0]	853563	1			T14	2		T16	3929		T112	47
all_pins[17]	values[0x0]	2319283	1			T32	1		T1	26		T11	1
all_pins[17]	values[0x1]	1421550	1			T1	17		T14	6		T16	6675
all_pins[17]	transitions[0x0=>0x1]	851416	1			T1	12		T14	6		T16	4227
all_pins[17]	transitions[0x1=>0x0]	842857	1			T14	7		T16	3961		T112	126
all_pins[18]	values[0x0]	2327155	1			T32	1		T1	31		T11	1
all_pins[18]	values[0x1]	1413678	1			T1	12		T14	8		T16	7125
all_pins[18]	transitions[0x0=>0x1]	843979	1			T14	8		T16	4206		T112	124
all_pins[18]	transitions[0x1=>0x0]	851851	1			T1	5		T14	6		T16	3756
all_pins[19]	values[0x0]	2322936	1			T32	1		T1	39		T11	1
all_pins[19]	values[0x1]	1417897	1			T1	4		T14	17		T16	6697
all_pins[19]	transitions[0x0=>0x1]	849501	1			T14	13		T16	3848		T112	127
all_pins[19]	transitions[0x1=>0x0]	845282	1			T1	8		T14	4		T16	4276
all_pins[20]	values[0x0]	2322813	1			T32	1		T1	38		T11	1
all_pins[20]	values[0x1]	1418020	1			T1	5		T14	13		T16	6896
all_pins[20]	transitions[0x0=>0x1]	848574	1			T1	1		T14	4		T16	4205
all_pins[20]	transitions[0x1=>0x0]	848451	1			T14	8		T16	4006		T112	85
all_pins[21]	values[0x0]	2328615	1			T32	1		T1	33		T11	1
all_pins[21]	values[0x1]	1412218	1			T1	10		T14	4		T16	6122
all_pins[21]	transitions[0x0=>0x1]	843947	1			T1	10		T16	3512		T112	49
all_pins[21]	transitions[0x1=>0x0]	849749	1			T1	5		T14	9		T16	4286
all_pins[22]	values[0x0]	2324034	1			T32	1		T1	34		T11	1
all_pins[22]	values[0x1]	1416799	1			T1	9		T14	9		T16	6727
all_pins[22]	transitions[0x0=>0x1]	852253	1			T1	9		T14	6		T16	4222
all_pins[22]	transitions[0x1=>0x0]	847672	1			T1	10		T14	1		T16	3617
all_pins[23]	values[0x0]	2328692	1			T32	1		T1	31		T11	1
all_pins[23]	values[0x1]	1412141	1			T1	12		T14	9		T16	7161
all_pins[23]	transitions[0x0=>0x1]	846095	1			T1	9		T14	4		T16	4313
all_pins[23]	transitions[0x1=>0x0]	850753	1			T1	6		T14	4		T16	3879
all_pins[24]	values[0x0]	2325684	1			T32	1		T1	30		T11	1
all_pins[24]	values[0x1]	1415149	1			T1	13		T14	4		T16	6621
all_pins[24]	transitions[0x0=>0x1]	849296	1			T1	6		T14	2		T16	3771
all_pins[24]	transitions[0x1=>0x0]	846288	1			T1	5		T14	7		T16	4311
all_pins[25]	values[0x0]	2323376	1			T32	1		T1	31		T11	1
all_pins[25]	values[0x1]	1417457	1			T1	12		T14	6		T16	6819
all_pins[25]	transitions[0x0=>0x1]	846047	1			T1	4		T14	4		T16	4224
all_pins[25]	transitions[0x1=>0x0]	843739	1			T1	5		T14	2		T16	4026
all_pins[26]	values[0x0]	2323771	1			T32	1		T1	40		T11	1
all_pins[26]	values[0x1]	1417062	1			T1	3		T14	5		T16	6545
all_pins[26]	transitions[0x0=>0x1]	849208	1			T1	1		T14	1		T16	3970
all_pins[26]	transitions[0x1=>0x0]	849603	1			T1	10		T14	2		T16	4244
all_pins[27]	values[0x0]	2327138	1			T32	1		T1	41		T11	1
all_pins[27]	values[0x1]	1413695	1			T1	2		T14	6		T16	6961
all_pins[27]	transitions[0x0=>0x1]	845690	1			T1	2		T14	5		T16	4236
all_pins[27]	transitions[0x1=>0x0]	849057	1			T1	3		T14	4		T16	3820
all_pins[28]	values[0x0]	2325618	1			T32	1		T1	38		T11	1
all_pins[28]	values[0x1]	1415215	1			T1	5		T14	9		T16	6785
all_pins[28]	transitions[0x0=>0x1]	848639	1			T1	5		T14	8		T16	3870
all_pins[28]	transitions[0x1=>0x0]	847119	1			T1	2		T14	5		T16	4046
all_pins[29]	values[0x0]	2324527	1			T32	1		T1	40		T11	1
all_pins[29]	values[0x1]	1416306	1			T1	3		T14	11		T16	6737
all_pins[29]	transitions[0x0=>0x1]	847552	1			T1	3		T14	8		T16	4004
all_pins[29]	transitions[0x1=>0x0]	846461	1			T1	5		T14	6		T16	4052
all_pins[30]	values[0x0]	2325491	1			T32	1		T1	29		T11	1
all_pins[30]	values[0x1]	1415342	1			T1	14		T16	6758		T112	166
all_pins[30]	transitions[0x0=>0x1]	846563	1			T1	14		T16	3990		T112	92
all_pins[30]	transitions[0x1=>0x0]	847527	1			T1	3		T14	11		T16	3969
all_pins[31]	values[0x0]	2323134	1			T32	1		T1	37		T11	1
all_pins[31]	values[0x1]	1417699	1			T1	6		T14	11		T16	6728
all_pins[31]	transitions[0x0=>0x1]	849501	1			T14	11		T16	3978		T112	109
all_pins[31]	transitions[0x1=>0x0]	847144	1			T1	8		T16	4008		T112	49