Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12716649	1			T32	231		T1	59		T11	483
all_values[1]	12716649	1			T32	231		T1	59		T11	483
all_values[2]	12716649	1			T32	231		T1	59		T11	483
all_values[3]	12716649	1			T32	231		T1	59		T11	483
all_values[4]	12716649	1			T32	231		T1	59		T11	483
all_values[5]	12716649	1			T32	231		T1	59		T11	483
all_values[6]	12716649	1			T32	231		T1	59		T11	483
all_values[7]	12716649	1			T32	231		T1	59		T11	483
all_values[8]	12716649	1			T32	231		T1	59		T11	483
all_values[9]	12716649	1			T32	231		T1	59		T11	483
all_values[10]	12716649	1			T32	231		T1	59		T11	483
all_values[11]	12716649	1			T32	231		T1	59		T11	483
all_values[12]	12716649	1			T32	231		T1	59		T11	483
all_values[13]	12716649	1			T32	231		T1	59		T11	483
all_values[14]	12716649	1			T32	231		T1	59		T11	483
all_values[15]	12716649	1			T32	231		T1	59		T11	483
all_values[16]	12716649	1			T32	231		T1	59		T11	483
all_values[17]	12716649	1			T32	231		T1	59		T11	483
all_values[18]	12716649	1			T32	231		T1	59		T11	483
all_values[19]	12716649	1			T32	231		T1	59		T11	483
all_values[20]	12716649	1			T32	231		T1	59		T11	483
all_values[21]	12716649	1			T32	231		T1	59		T11	483
all_values[22]	12716649	1			T32	231		T1	59		T11	483
all_values[23]	12716649	1			T32	231		T1	59		T11	483
all_values[24]	12716649	1			T32	231		T1	59		T11	483
all_values[25]	12716649	1			T32	231		T1	59		T11	483
all_values[26]	12716649	1			T32	231		T1	59		T11	483
all_values[27]	12716649	1			T32	231		T1	59		T11	483
all_values[28]	12716649	1			T32	231		T1	59		T11	483
all_values[29]	12716649	1			T32	231		T1	59		T11	483
all_values[30]	12716649	1			T32	231		T1	59		T11	483
all_values[31]	12716649	1			T32	231		T1	59		T11	483

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238164274

1

T32

7392

T1

1262

T11

15456

auto[1]

168768494

1

T1

626

T14

737

T16

689528

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101821663

1

T32

7392

T1

1215

T11

15456

auto[1]

305111105

1

T1

673

T14

542

T16

123719

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

402447633

1

T32

7392

T1

1782

T11

15456

auto[1]

4485135

1

T1

106

T14

122

T16

18803

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2675036	1			T32	231		T1	30		T11	483
all_values[0]	auto[0]	auto[0]	auto[1]	4700521	1			T1	9		T14	1		T16	18827
all_values[0]	auto[0]	auto[1]	auto[0]	505922	1			T1	15		T14	22		T16	2250
all_values[0]	auto[0]	auto[1]	auto[1]	4694970	1			T1	1		T14	4		T16	19514
all_values[0]	auto[1]	auto[0]	auto[1]	70168	1			T1	3		T14	5		T16	283
all_values[0]	auto[1]	auto[1]	auto[1]	70032	1			T1	1		T16	309		T2	20
all_values[1]	auto[0]	auto[0]	auto[0]	2671048	1			T32	231		T1	27		T11	483
all_values[1]	auto[0]	auto[0]	auto[1]	4721282	1			T1	2		T14	10		T16	20184
all_values[1]	auto[0]	auto[1]	auto[0]	511270	1			T1	10		T14	21		T16	2364
all_values[1]	auto[0]	auto[1]	auto[1]	4673256	1			T1	19		T14	2		T16	17883
all_values[1]	auto[1]	auto[0]	auto[1]	70098	1			T14	3		T16	297		T2	9
all_values[1]	auto[1]	auto[1]	auto[1]	69695	1			T1	1		T14	2		T16	279
all_values[2]	auto[0]	auto[0]	auto[0]	2673995	1			T32	231		T1	33		T11	483
all_values[2]	auto[0]	auto[0]	auto[1]	4711194	1			T1	6		T14	4		T16	18442
all_values[2]	auto[0]	auto[1]	auto[0]	517350	1			T1	10		T14	17		T16	2462
all_values[2]	auto[0]	auto[1]	auto[1]	4673815	1			T1	7		T14	6		T16	19614
all_values[2]	auto[1]	auto[0]	auto[1]	70911	1			T1	1		T14	2		T16	300
all_values[2]	auto[1]	auto[1]	auto[1]	69384	1			T1	2		T16	277		T2	20
all_values[3]	auto[0]	auto[0]	auto[0]	2673319	1			T32	231		T1	16		T11	483
all_values[3]	auto[0]	auto[0]	auto[1]	4681448	1			T1	8		T14	10		T16	19472
all_values[3]	auto[0]	auto[1]	auto[0]	516884	1			T1	12		T14	18		T16	2056
all_values[3]	auto[0]	auto[1]	auto[1]	4704567	1			T1	18		T16	19071		T112	429
all_values[3]	auto[1]	auto[0]	auto[1]	70459	1			T1	1		T14	4		T16	293
all_values[3]	auto[1]	auto[1]	auto[1]	69972	1			T1	4		T16	310		T2	7
all_values[4]	auto[0]	auto[0]	auto[0]	2671638	1			T32	231		T1	28		T11	483
all_values[4]	auto[0]	auto[0]	auto[1]	4711273	1			T1	7		T14	3		T16	18750
all_values[4]	auto[0]	auto[1]	auto[0]	514680	1			T1	23		T14	14		T16	2831
all_values[4]	auto[0]	auto[1]	auto[1]	4678808	1			T14	9		T16	19195		T112	518
all_values[4]	auto[1]	auto[0]	auto[1]	70393	1			T1	1		T14	2		T16	301
all_values[4]	auto[1]	auto[1]	auto[1]	69857	1			T14	1		T16	304		T2	24
all_values[5]	auto[0]	auto[0]	auto[0]	2671256	1			T32	231		T1	38		T11	483
all_values[5]	auto[0]	auto[0]	auto[1]	4724375	1			T1	12		T14	9		T16	18838
all_values[5]	auto[0]	auto[1]	auto[0]	509189	1			T1	4		T14	18		T16	2222
all_values[5]	auto[0]	auto[1]	auto[1]	4671592	1			T1	3		T14	6		T16	19212
all_values[5]	auto[1]	auto[0]	auto[1]	70341	1			T1	2		T14	1		T16	303
all_values[5]	auto[1]	auto[1]	auto[1]	69896	1			T14	1		T16	278		T2	16
all_values[6]	auto[0]	auto[0]	auto[0]	2663090	1			T32	231		T1	27		T11	483
all_values[6]	auto[0]	auto[0]	auto[1]	4714582	1			T1	12		T14	7		T16	19043
all_values[6]	auto[0]	auto[1]	auto[0]	509229	1			T1	12		T14	30		T16	2067
all_values[6]	auto[0]	auto[1]	auto[1]	4689840	1			T1	3		T14	4		T16	19421
all_values[6]	auto[1]	auto[0]	auto[1]	69892	1			T1	2		T14	1		T16	286
all_values[6]	auto[1]	auto[1]	auto[1]	70016	1			T1	3		T14	1		T16	307
all_values[7]	auto[0]	auto[0]	auto[0]	2666299	1			T32	231		T1	19		T11	483
all_values[7]	auto[0]	auto[0]	auto[1]	4703966	1			T1	15		T14	11		T16	19456
all_values[7]	auto[0]	auto[1]	auto[0]	510520	1			T1	13		T14	6		T16	2401
all_values[7]	auto[0]	auto[1]	auto[1]	4696414	1			T1	6		T14	7		T16	18752
all_values[7]	auto[1]	auto[0]	auto[1]	69903	1			T1	3		T14	5		T16	289
all_values[7]	auto[1]	auto[1]	auto[1]	69547	1			T1	3		T14	2		T16	281
all_values[8]	auto[0]	auto[0]	auto[0]	2674460	1			T32	231		T1	29		T11	483
all_values[8]	auto[0]	auto[0]	auto[1]	4685737	1			T1	7		T14	6		T16	18990
all_values[8]	auto[0]	auto[1]	auto[0]	509911	1			T1	10		T14	6		T16	2655
all_values[8]	auto[0]	auto[1]	auto[1]	4706708	1			T1	9		T14	5		T16	18550
all_values[8]	auto[1]	auto[0]	auto[1]	70043	1			T1	2		T14	3		T16	314
all_values[8]	auto[1]	auto[1]	auto[1]	69790	1			T1	2		T14	1		T16	285
all_values[9]	auto[0]	auto[0]	auto[0]	2667882	1			T32	231		T1	27		T11	483
all_values[9]	auto[0]	auto[0]	auto[1]	4693138	1			T1	17		T14	3		T16	19721
all_values[9]	auto[0]	auto[1]	auto[0]	503787	1			T1	6		T14	21		T16	2211
all_values[9]	auto[0]	auto[1]	auto[1]	4711660	1			T1	3		T14	1		T16	18235
all_values[9]	auto[1]	auto[0]	auto[1]	69991	1			T1	4		T14	2		T16	300
all_values[9]	auto[1]	auto[1]	auto[1]	70191	1			T1	2		T14	1		T16	321
all_values[10]	auto[0]	auto[0]	auto[0]	2668738	1			T32	231		T1	25		T11	483
all_values[10]	auto[0]	auto[0]	auto[1]	4702510	1			T1	15		T14	4		T16	19414
all_values[10]	auto[0]	auto[1]	auto[0]	513302	1			T1	7		T14	20		T16	2427
all_values[10]	auto[0]	auto[1]	auto[1]	4691607	1			T1	9		T14	5		T16	18559
all_values[10]	auto[1]	auto[0]	auto[1]	70528	1			T1	2		T14	5		T16	277
all_values[10]	auto[1]	auto[1]	auto[1]	69964	1			T1	1		T14	1		T16	271
all_values[11]	auto[0]	auto[0]	auto[0]	2659908	1			T32	231		T1	25		T11	483
all_values[11]	auto[0]	auto[0]	auto[1]	4686204	1			T1	17		T14	16		T16	19323
all_values[11]	auto[0]	auto[1]	auto[0]	518136	1			T1	3		T14	11		T16	2382
all_values[11]	auto[0]	auto[1]	auto[1]	4712190	1			T1	11		T14	5		T16	18691
all_values[11]	auto[1]	auto[0]	auto[1]	69759	1			T1	1		T14	4		T16	259
all_values[11]	auto[1]	auto[1]	auto[1]	70452	1			T1	2		T16	305		T2	12
all_values[12]	auto[0]	auto[0]	auto[0]	2674219	1			T32	231		T1	36		T11	483
all_values[12]	auto[0]	auto[0]	auto[1]	4715771	1			T1	6		T14	12		T16	19929
all_values[12]	auto[0]	auto[1]	auto[0]	505888	1			T1	10		T14	16		T16	2271
all_values[12]	auto[0]	auto[1]	auto[1]	4680883	1			T1	4		T14	8		T16	18526
all_values[12]	auto[1]	auto[0]	auto[1]	70905	1			T1	2		T14	1		T16	276
all_values[12]	auto[1]	auto[1]	auto[1]	68983	1			T1	1		T14	3		T16	301
all_values[13]	auto[0]	auto[0]	auto[0]	2675096	1			T32	231		T1	24		T11	483
all_values[13]	auto[0]	auto[0]	auto[1]	4694009	1			T1	11		T14	9		T16	18963
all_values[13]	auto[0]	auto[1]	auto[0]	513380	1			T1	12		T14	21		T16	2192
all_values[13]	auto[0]	auto[1]	auto[1]	4694114	1			T1	9		T16	19534		T112	431
all_values[13]	auto[1]	auto[0]	auto[1]	70042	1			T1	2		T14	2		T16	273
all_values[13]	auto[1]	auto[1]	auto[1]	70008	1			T1	1		T16	296		T2	24
all_values[14]	auto[0]	auto[0]	auto[0]	2668560	1			T32	231		T1	30		T11	483
all_values[14]	auto[0]	auto[0]	auto[1]	4685217	1			T1	20		T14	10		T16	19052
all_values[14]	auto[0]	auto[1]	auto[0]	522843	1			T14	28		T16	2490		T112	70
all_values[14]	auto[0]	auto[1]	auto[1]	4700147	1			T1	5		T16	18622		T112	284
all_values[14]	auto[1]	auto[0]	auto[1]	70211	1			T1	3		T14	5		T16	298
all_values[14]	auto[1]	auto[1]	auto[1]	69671	1			T1	1		T14	1		T16	301
all_values[15]	auto[0]	auto[0]	auto[0]	2661267	1			T32	231		T1	29		T11	483
all_values[15]	auto[0]	auto[0]	auto[1]	4693046	1			T1	5		T14	13		T16	19367
all_values[15]	auto[0]	auto[1]	auto[0]	514068	1			T1	23		T14	15		T16	2345
all_values[15]	auto[0]	auto[1]	auto[1]	4708314	1			T14	1		T16	18705		T112	245
all_values[15]	auto[1]	auto[0]	auto[1]	69948	1			T1	2		T14	2		T16	308
all_values[15]	auto[1]	auto[1]	auto[1]	70006	1			T14	1		T16	311		T2	15
all_values[16]	auto[0]	auto[0]	auto[0]	2672104	1			T32	231		T1	29		T11	483
all_values[16]	auto[0]	auto[0]	auto[1]	4682515	1			T1	11		T14	11		T16	19466
all_values[16]	auto[0]	auto[1]	auto[0]	514739	1			T1	12		T14	16		T16	2389
all_values[16]	auto[0]	auto[1]	auto[1]	4707017	1			T1	3		T14	7		T16	18454
all_values[16]	auto[1]	auto[0]	auto[1]	70321	1			T1	2		T14	1		T16	266
all_values[16]	auto[1]	auto[1]	auto[1]	69953	1			T1	2		T16	316		T2	18
all_values[17]	auto[0]	auto[0]	auto[0]	2662380	1			T32	231		T1	20		T11	483
all_values[17]	auto[0]	auto[0]	auto[1]	4708474	1			T1	10		T14	11		T16	18935
all_values[17]	auto[0]	auto[1]	auto[0]	510484	1			T1	8		T14	19		T16	2477
all_values[17]	auto[0]	auto[1]	auto[1]	4695034	1			T1	17		T14	4		T16	18874
all_values[17]	auto[1]	auto[0]	auto[1]	70470	1			T1	1		T14	3		T16	310
all_values[17]	auto[1]	auto[1]	auto[1]	69807	1			T1	3		T16	274		T2	10
all_values[18]	auto[0]	auto[0]	auto[0]	2678352	1			T32	231		T1	19		T11	483
all_values[18]	auto[0]	auto[0]	auto[1]	4705306	1			T14	1		T16	17581		T112	376
all_values[18]	auto[0]	auto[1]	auto[0]	512948	1			T1	26		T14	24		T16	2635
all_values[18]	auto[0]	auto[1]	auto[1]	4679779	1			T1	13		T14	8		T16	20145
all_values[18]	auto[1]	auto[0]	auto[1]	69833	1			T14	3		T16	296		T2	11
all_values[18]	auto[1]	auto[1]	auto[1]	70431	1			T1	1		T14	1		T16	298
all_values[19]	auto[0]	auto[0]	auto[0]	2675157	1			T32	231		T1	32		T11	483
all_values[19]	auto[0]	auto[0]	auto[1]	4707288	1			T1	16		T14	11		T16	19467
all_values[19]	auto[0]	auto[1]	auto[0]	511627	1			T14	9		T16	2304		T112	76
all_values[19]	auto[0]	auto[1]	auto[1]	4681854	1			T1	6		T14	15		T16	18523
all_values[19]	auto[1]	auto[0]	auto[1]	70757	1			T1	5		T14	2		T16	323
all_values[19]	auto[1]	auto[1]	auto[1]	69966	1			T16	264		T2	14		T113	189
all_values[20]	auto[0]	auto[0]	auto[0]	2660551	1			T32	231		T1	28		T11	483
all_values[20]	auto[0]	auto[0]	auto[1]	4666083	1			T1	14		T14	2		T16	19675
all_values[20]	auto[0]	auto[1]	auto[0]	507062	1			T1	11		T14	24		T16	1967
all_values[20]	auto[0]	auto[1]	auto[1]	4742863	1			T1	6		T14	12		T16	18803
all_values[20]	auto[1]	auto[0]	auto[1]	70392	1			T14	1		T16	278		T2	23
all_values[20]	auto[1]	auto[1]	auto[1]	69698	1			T14	1		T16	307		T2	11
all_values[21]	auto[0]	auto[0]	auto[0]	2667390	1			T32	231		T1	25		T11	483
all_values[21]	auto[0]	auto[0]	auto[1]	4706229	1			T1	8		T14	12		T16	20462
all_values[21]	auto[0]	auto[1]	auto[0]	508263	1			T1	13		T14	6		T16	2291
all_values[21]	auto[0]	auto[1]	auto[1]	4694484	1			T1	8		T14	2		T16	17397
all_values[21]	auto[1]	auto[0]	auto[1]	70558	1			T1	2		T14	2		T16	308
all_values[21]	auto[1]	auto[1]	auto[1]	69725	1			T1	3		T14	1		T16	289
all_values[22]	auto[0]	auto[0]	auto[0]	2663709	1			T32	231		T1	28		T11	483
all_values[22]	auto[0]	auto[0]	auto[1]	4715487	1			T1	6		T14	6		T16	18826
all_values[22]	auto[0]	auto[1]	auto[0]	515756	1			T1	11		T14	13		T16	2612
all_values[22]	auto[0]	auto[1]	auto[1]	4681446	1			T1	10		T14	8		T16	19061
all_values[22]	auto[1]	auto[0]	auto[1]	70129	1			T1	2		T14	5		T16	309
all_values[22]	auto[1]	auto[1]	auto[1]	70122	1			T1	2		T14	1		T16	274
all_values[23]	auto[0]	auto[0]	auto[0]	2672890	1			T32	231		T1	32		T11	483
all_values[23]	auto[0]	auto[0]	auto[1]	4723224	1			T1	8		T14	6		T16	18169
all_values[23]	auto[0]	auto[1]	auto[0]	503317	1			T1	3		T14	15		T16	2325
all_values[23]	auto[0]	auto[1]	auto[1]	4676625	1			T1	12		T14	7		T16	20256
all_values[23]	auto[1]	auto[0]	auto[1]	70675	1			T1	2		T14	4		T16	294
all_values[23]	auto[1]	auto[1]	auto[1]	69918	1			T1	2		T14	1		T16	286
all_values[24]	auto[0]	auto[0]	auto[0]	2667925	1			T32	231		T1	25		T11	483
all_values[24]	auto[0]	auto[0]	auto[1]	4688383	1			T1	12		T14	7		T16	19913
all_values[24]	auto[0]	auto[1]	auto[0]	519150	1			T1	8		T14	19		T16	2309
all_values[24]	auto[0]	auto[1]	auto[1]	4700989	1			T1	13		T14	3		T16	18066
all_values[24]	auto[1]	auto[0]	auto[1]	70176	1			T14	1		T16	304		T2	17
all_values[24]	auto[1]	auto[1]	auto[1]	70026	1			T1	1		T14	1		T16	280
all_values[25]	auto[0]	auto[0]	auto[0]	2669286	1			T32	231		T1	19		T11	483
all_values[25]	auto[0]	auto[0]	auto[1]	4709333	1			T1	6		T14	8		T16	19149
all_values[25]	auto[0]	auto[1]	auto[0]	511622	1			T1	21		T14	8		T16	2296
all_values[25]	auto[0]	auto[1]	auto[1]	4686115	1			T1	9		T14	5		T16	19221
all_values[25]	auto[1]	auto[0]	auto[1]	70477	1			T14	5		T16	263		T2	23
all_values[25]	auto[1]	auto[1]	auto[1]	69816	1			T1	4		T14	1		T16	344
all_values[26]	auto[0]	auto[0]	auto[0]	2663872	1			T32	231		T1	27		T11	483
all_values[26]	auto[0]	auto[0]	auto[1]	4700231	1			T1	21		T14	8		T16	19580
all_values[26]	auto[0]	auto[1]	auto[0]	510015	1			T1	1		T14	4		T16	2429
all_values[26]	auto[0]	auto[1]	auto[1]	4702533	1			T1	5		T14	4		T16	18157
all_values[26]	auto[1]	auto[0]	auto[1]	70542	1			T1	5		T14	4		T16	313
all_values[26]	auto[1]	auto[1]	auto[1]	69456	1			T14	1		T16	289		T2	10
all_values[27]	auto[0]	auto[0]	auto[0]	2670817	1			T32	231		T1	28		T11	483
all_values[27]	auto[0]	auto[0]	auto[1]	4735046	1			T1	4		T14	10		T16	17992
all_values[27]	auto[0]	auto[1]	auto[0]	519188	1			T1	25		T14	4		T16	2615
all_values[27]	auto[0]	auto[1]	auto[1]	4650988	1			T1	2		T14	6		T16	19810
all_values[27]	auto[1]	auto[0]	auto[1]	70542	1			T14	4		T16	314		T2	13
all_values[27]	auto[1]	auto[1]	auto[1]	70068	1			T14	1		T16	299		T2	18
all_values[28]	auto[0]	auto[0]	auto[0]	2666980	1			T32	231		T1	33		T11	483
all_values[28]	auto[0]	auto[0]	auto[1]	4722969	1			T1	9		T14	8		T16	18800
all_values[28]	auto[0]	auto[1]	auto[0]	513429	1			T1	6		T14	19		T16	2088
all_values[28]	auto[0]	auto[1]	auto[1]	4673098	1			T1	6		T14	7		T16	19524
all_values[28]	auto[1]	auto[0]	auto[1]	70383	1			T1	5		T14	2		T16	298
all_values[28]	auto[1]	auto[1]	auto[1]	69790	1			T14	1		T16	277		T2	13
all_values[29]	auto[0]	auto[0]	auto[0]	2675257	1			T32	231		T1	38		T11	483
all_values[29]	auto[0]	auto[0]	auto[1]	4720710	1			T1	13		T14	6		T16	19098
all_values[29]	auto[0]	auto[1]	auto[0]	516400	1			T1	2		T14	25		T16	2103
all_values[29]	auto[0]	auto[1]	auto[1]	4664316	1			T1	3		T14	9		T16	18957
all_values[29]	auto[1]	auto[0]	auto[1]	70659	1			T1	2		T14	4		T16	279
all_values[29]	auto[1]	auto[1]	auto[1]	69307	1			T1	1		T14	2		T16	314
all_values[30]	auto[0]	auto[0]	auto[0]	2670128	1			T32	231		T1	17		T11	483
all_values[30]	auto[0]	auto[0]	auto[1]	4691129	1			T1	17		T14	3		T16	19219
all_values[30]	auto[0]	auto[1]	auto[0]	512608	1			T1	7		T14	26		T16	2308
all_values[30]	auto[0]	auto[1]	auto[1]	4702557	1			T1	14		T16	18740		T112	408
all_values[30]	auto[1]	auto[0]	auto[1]	70176	1			T1	3		T14	3		T16	263
all_values[30]	auto[1]	auto[1]	auto[1]	70051	1			T1	1		T16	296		T2	19
all_values[31]	auto[0]	auto[0]	auto[0]	2669084	1			T32	231		T1	30		T11	483
all_values[31]	auto[0]	auto[0]	auto[1]	4685726	1			T1	4		T14	11		T16	19343
all_values[31]	auto[0]	auto[1]	auto[0]	517003	1			T1	18		T14	23		T16	2375
all_values[31]	auto[0]	auto[1]	auto[1]	4704981	1			T1	5		T14	11		T16	18873
all_values[31]	auto[1]	auto[0]	auto[1]	70493	1			T1	1		T14	3		T16	294
all_values[31]	auto[1]	auto[1]	auto[1]	69362	1			T1	1		T14	1		T16	291

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal