Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[1]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[2]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[3]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[4]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[5]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[6]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[7]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[8]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[9]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[10]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[11]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[12]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[13]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[14]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[15]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[16]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[17]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[18]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[19]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[20]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[21]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[22]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[23]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[24]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[25]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[26]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[27]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[28]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[29]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[30]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[31]	12528923	1			T32	387		T1	127		T11	883

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240505569

1

T32

8632

T1

2116

T11

20395

auto[1]

160419967

1

T32

3752

T1

1948

T11

7861

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322565648

1

T32

7331

T1

3737

T11

15181

auto[1]

78359888

1

T32

5053

T1

327

T11

13075

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299495284

1

T32

7290

T1

2997

T11

15461

auto[1]

101430252

1

T32

5094

T1

1067

T11

12795

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4701458	1			T32	115		T1	48		T11	244
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3429726	1			T32	34		T1	32		T11	47
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1231832	1			T32	86		T1	9		T11	228
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1585535	1			T32	78		T1	5		T11	160
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	361606	1			T1	10		T13	5		T14	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1218766	1			T32	74		T1	23		T11	204
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4700302	1			T32	116		T1	46		T11	260
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3427548	1			T32	33		T1	39		T11	54
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1235644	1			T32	106		T1	3		T11	173
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1581532	1			T32	62		T1	19		T11	196
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	364075	1			T1	9		T13	3		T14	16
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1219822	1			T32	70		T1	11		T11	200
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4696250	1			T32	100		T1	30		T11	227
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3429573	1			T32	34		T1	35		T11	43
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1233117	1			T32	105		T11	234		T12	200
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1585977	1			T32	68		T1	28		T11	176
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	361298	1			T1	15		T13	7		T14	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1222708	1			T32	80		T1	19		T11	203
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4704913	1			T32	122		T1	35		T11	199
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3424911	1			T32	31		T1	66		T11	47
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1231094	1			T32	86		T11	213		T12	212
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1586869	1			T32	86		T1	11		T11	184
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	360008	1			T1	13		T13	14		T14	15
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1221128	1			T32	62		T1	2		T11	240
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4684646	1			T32	124		T1	60		T11	234
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3434852	1			T32	35		T1	40		T11	36
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1234366	1			T32	80		T11	190		T12	188
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1593496	1			T32	64		T1	14		T11	216
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	361704	1			T1	5		T13	12		T14	13
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1219859	1			T32	84		T1	8		T11	207
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4693720	1			T32	104		T1	38		T11	252
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3428801	1			T32	36		T1	39		T11	34
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1233365	1			T32	63		T11	221		T12	158
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1593778	1			T32	98		T1	19		T11	192
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	361301	1			T1	19		T13	6		T14	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1217958	1			T32	86		T1	12		T11	184
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4697291	1			T32	96		T1	46		T11	269
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3432103	1			T32	45		T1	50		T11	51
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1230903	1			T32	74		T1	8		T11	208
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1587819	1			T32	98		T1	6		T11	178
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	359634	1			T1	10		T13	6		T14	3
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1221173	1			T32	74		T1	7		T11	177
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4689790	1			T32	119		T1	39		T11	223
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3436467	1			T32	39		T1	37		T11	39
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1233405	1			T32	78		T11	201		T12	179
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1589470	1			T32	80		T1	32		T11	168
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	361611	1			T1	13		T13	2		T14	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1218180	1			T32	71		T1	6		T11	252
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4690235	1			T32	114		T1	42		T11	272
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3436340	1			T32	38		T1	24		T11	50
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1230852	1			T32	72		T11	205		T12	224
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1589216	1			T32	82		T1	30		T11	192
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	364173	1			T1	11		T13	9		T14	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1218107	1			T32	81		T1	20		T11	164
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4703542	1			T32	104		T1	58		T11	203
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3419753	1			T32	40		T1	49		T11	41
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1233625	1			T32	76		T11	228		T12	186
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1589261	1			T32	111		T1	6		T11	215
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	361251	1			T1	7		T13	10		T14	2
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1221491	1			T32	56		T1	7		T11	196
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4688943	1			T32	129		T1	56		T11	234
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3433485	1			T32	40		T1	23		T11	44
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1229140	1			T32	78		T1	7		T11	214
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1591243	1			T32	54		T1	8		T11	200
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	363940	1			T1	19		T13	10		T14	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1222172	1			T32	86		T1	14		T11	191
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4687673	1			T32	130		T1	44		T11	249
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3434625	1			T32	35		T1	52		T11	42
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1233164	1			T32	62		T11	216		T12	173
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1592484	1			T32	94		T1	17		T11	180
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	359287	1			T1	7		T13	12		T14	7
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1221690	1			T32	66		T1	7		T11	196
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4693896	1			T32	128		T1	39		T11	237
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3438448	1			T32	40		T1	54		T11	45
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1231837	1			T32	75		T11	182		T12	219
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1586758	1			T32	90		T1	20		T11	201
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	361041	1			T1	10		T13	9		T14	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1216943	1			T32	54		T1	4		T11	218
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4698012	1			T32	118		T1	33		T11	235
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3430531	1			T32	44		T1	47		T11	41
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1232798	1			T32	46		T11	200		T12	207
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1585435	1			T32	101		T1	24		T11	215
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	360992	1			T1	18		T13	14		T14	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1221155	1			T32	78		T1	5		T11	192
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4683677	1			T32	126		T1	61		T11	245
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3438844	1			T32	34		T1	35		T11	39
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1230906	1			T32	67		T1	6		T11	215
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1589355	1			T32	82		T1	15		T11	226
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	360361	1			T1	6		T13	6		T14	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1225780	1			T32	78		T1	4		T11	158
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4695222	1			T32	106		T1	33		T11	198
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3442518	1			T32	38		T1	64		T11	42
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1234591	1			T32	91		T11	195		T12	190
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1581520	1			T32	86		T1	9		T11	218
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	359340	1			T1	8		T13	7		T14	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1215732	1			T32	66		T1	13		T11	230
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4696005	1			T32	99		T1	70		T11	225
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3440445	1			T32	39		T1	21		T11	38
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1231046	1			T32	98		T1	2		T11	224
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1585966	1			T32	68		T1	11		T11	176
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	361670	1			T1	10		T13	2		T14	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1213791	1			T32	83		T1	13		T11	220
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4702162	1			T32	96		T1	61		T11	202
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3429889	1			T32	42		T1	19		T11	46
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1228204	1			T32	58		T1	6		T11	207
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1592780	1			T32	101		T1	28		T11	190
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	361465	1			T1	7		T13	1		T14	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1214423	1			T32	90		T1	6		T11	238
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4701821	1			T32	115		T1	16		T11	234
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3429423	1			T32	33		T1	57		T11	43
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1231736	1			T32	60		T1	2		T11	218
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1589892	1			T32	79		T1	24		T11	206
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	361127	1			T1	20		T13	10		T14	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1214924	1			T32	100		T1	8		T11	182
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4696202	1			T32	143		T1	63		T11	229
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3425623	1			T32	34		T1	44		T11	37
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1228794	1			T32	86		T1	2		T11	209
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1589376	1			T32	58		T1	5		T11	196
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	365588	1			T1	11		T13	4		T14	12
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1223340	1			T32	66		T1	2		T11	212
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4699732	1			T32	105		T1	42		T11	245
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3435101	1			T32	39		T1	36		T11	43
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1232318	1			T32	56		T1	14		T11	220
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1584894	1			T32	94		T1	17		T11	186
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	361929	1			T1	12		T13	4		T16	7437
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1214949	1			T32	93		T1	6		T11	189
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4701158	1			T32	118		T1	28		T11	276
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3429854	1			T32	36		T1	53		T11	36
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1223310	1			T32	82		T1	10		T11	164
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1593295	1			T32	65		T1	21		T11	210
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	361378	1			T1	13		T13	10		T14	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1219928	1			T32	86		T1	2		T11	197
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4690525	1			T32	94		T1	39		T11	260
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3438235	1			T32	35		T1	59		T11	38
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1230443	1			T32	78		T11	213		T12	194
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1586861	1			T32	66		T1	10		T11	188
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	363347	1			T1	10		T13	3		T14	21
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1219512	1			T32	114		T1	9		T11	184
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4707383	1			T32	100		T1	56		T11	243
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3425761	1			T32	37		T1	39		T11	39
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1227761	1			T32	62		T1	5		T11	157
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1585331	1			T32	94		T1	16		T11	212
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	362723	1			T1	11		T13	2		T14	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1219964	1			T32	94		T11	232		T12	190
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4694996	1			T32	89		T1	54		T11	233
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3432835	1			T32	33		T1	49		T11	39
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1226952	1			T32	102		T1	2		T11	207
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1592009	1			T32	72		T1	22		T11	214
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	366437	1			T13	9		T14	1		T16	8134
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1215694	1			T32	91		T11	190		T12	191
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4696136	1			T32	116		T1	64		T11	236
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3434781	1			T32	36		T1	43		T11	42
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1228584	1			T32	76		T1	2		T11	250
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1596141	1			T32	58		T1	16		T11	172
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	361207	1			T1	2		T13	8		T14	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1212074	1			T32	101		T11	183		T12	216
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4693897	1			T32	125		T1	43		T11	225
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3439623	1			T32	37		T1	58		T11	36
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1228311	1			T32	81		T1	3		T11	226
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1593916	1			T32	80		T1	14		T11	178
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	359471	1			T1	3		T13	6		T14	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1213705	1			T32	64		T1	6		T11	218
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4699513	1			T32	122		T1	63		T11	236
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3425582	1			T32	34		T1	37		T11	42
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1226273	1			T32	84		T11	178		T12	174
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1596337	1			T32	62		T1	4		T11	216
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	362858	1			T1	18		T13	12		T14	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1218360	1			T32	85		T1	5		T11	211
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4694573	1			T32	89		T1	46		T11	228
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3433540	1			T32	39		T1	53		T11	44
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1225902	1			T32	99		T1	2		T11	180
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1596103	1			T32	62		T1	3		T11	218
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	360292	1			T1	16		T13	11		T14	6
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1218513	1			T32	98		T1	7		T11	213
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4687401	1			T32	118		T1	67		T11	185
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3443289	1			T32	34		T1	41		T11	46
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1226280	1			T32	79		T11	228		T12	196
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1594282	1			T32	78		T1	6		T11	184
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	360674	1			T1	9		T13	5		T16	7420
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1216997	1			T32	78		T1	4		T11	240
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4695634	1			T32	123		T1	41		T11	272
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3440138	1			T32	41		T1	45		T11	44
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1227995	1			T32	80		T11	187		T12	180
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1591539	1			T32	70		T1	18		T11	218
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	362877	1			T1	17		T13	10		T14	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1210740	1			T32	73		T1	6		T11	162
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4698995	1			T32	112		T1	73		T11	255
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3433924	1			T32	42		T1	32		T11	33
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1228465	1			T32	62		T1	8		T11	164
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1588383	1			T32	88		T1	13		T11	194
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	361859	1			T1	1		T13	4		T14	12
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1217297	1			T32	83		T11	237		T12	195

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal