Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[1]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[2]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[3]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[4]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[5]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[6]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[7]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[8]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[9]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[10]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[11]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[12]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[13]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[14]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[15]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[16]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[17]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[18]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[19]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[20]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[21]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[22]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[23]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[24]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[25]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[26]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[27]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[28]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[29]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[30]	12528923	1			T32	387		T1	127		T11	883
bins_for_gpio_bits[31]	12528923	1			T32	387		T1	127		T11	883

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240505569

1

T32

8632

T1

2116

T11

20395

auto[1]

160419967

1

T32

3752

T1

1948

T11

7861

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240496855

1

T32

8623

T1

2116

T11

20385

auto[1]

160428681

1

T32

3761

T1

1948

T11

7871

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7301392	1			T32	260		T1	62		T11	579
bins_for_gpio_bits[0]	auto[0]	auto[1]	217164	1			T32	19		T11	53		T12	55
bins_for_gpio_bits[0]	auto[1]	auto[0]	217433	1			T32	19		T11	53		T12	55
bins_for_gpio_bits[0]	auto[1]	auto[1]	4792934	1			T32	89		T1	65		T11	198
bins_for_gpio_bits[1]	auto[0]	auto[0]	7300114	1			T32	265		T1	68		T11	578
bins_for_gpio_bits[1]	auto[0]	auto[1]	217080	1			T32	19		T11	51		T12	50
bins_for_gpio_bits[1]	auto[1]	auto[0]	217364	1			T32	19		T11	51		T12	50
bins_for_gpio_bits[1]	auto[1]	auto[1]	4794365	1			T32	84		T1	59		T11	203
bins_for_gpio_bits[2]	auto[0]	auto[0]	7297569	1			T32	251		T1	58		T11	586
bins_for_gpio_bits[2]	auto[0]	auto[1]	217493	1			T32	22		T11	50		T12	47
bins_for_gpio_bits[2]	auto[1]	auto[0]	217775	1			T32	22		T11	51		T12	48
bins_for_gpio_bits[2]	auto[1]	auto[1]	4796086	1			T32	92		T1	69		T11	196
bins_for_gpio_bits[3]	auto[0]	auto[0]	7305182	1			T32	275		T1	46		T11	532
bins_for_gpio_bits[3]	auto[0]	auto[1]	217436	1			T32	19		T11	64		T12	46
bins_for_gpio_bits[3]	auto[1]	auto[0]	217694	1			T32	19		T11	64		T12	47
bins_for_gpio_bits[3]	auto[1]	auto[1]	4788611	1			T32	74		T1	81		T11	223
bins_for_gpio_bits[4]	auto[0]	auto[0]	7294739	1			T32	245		T1	74		T11	582
bins_for_gpio_bits[4]	auto[0]	auto[1]	217477	1			T32	23		T11	57		T12	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	217769	1			T32	23		T11	58		T12	51
bins_for_gpio_bits[4]	auto[1]	auto[1]	4798938	1			T32	96		T1	53		T11	186
bins_for_gpio_bits[5]	auto[0]	auto[0]	7303290	1			T32	246		T1	57		T11	614
bins_for_gpio_bits[5]	auto[0]	auto[1]	217346	1			T32	19		T11	51		T12	45
bins_for_gpio_bits[5]	auto[1]	auto[0]	217573	1			T32	19		T11	51		T12	46
bins_for_gpio_bits[5]	auto[1]	auto[1]	4790714	1			T32	103		T1	70		T11	167
bins_for_gpio_bits[6]	auto[0]	auto[0]	7298825	1			T32	250		T1	60		T11	606
bins_for_gpio_bits[6]	auto[0]	auto[1]	216888	1			T32	18		T11	48		T12	54
bins_for_gpio_bits[6]	auto[1]	auto[0]	217188	1			T32	18		T11	49		T12	54
bins_for_gpio_bits[6]	auto[1]	auto[1]	4796022	1			T32	101		T1	67		T11	180
bins_for_gpio_bits[7]	auto[0]	auto[0]	7294858	1			T32	260		T1	71		T11	540
bins_for_gpio_bits[7]	auto[0]	auto[1]	217543	1			T32	16		T11	52		T12	45
bins_for_gpio_bits[7]	auto[1]	auto[0]	217807	1			T32	17		T11	52		T12	45
bins_for_gpio_bits[7]	auto[1]	auto[1]	4798715	1			T32	94		T1	56		T11	239
bins_for_gpio_bits[8]	auto[0]	auto[0]	7293262	1			T32	247		T1	72		T11	618
bins_for_gpio_bits[8]	auto[0]	auto[1]	216761	1			T32	20		T11	51		T12	52
bins_for_gpio_bits[8]	auto[1]	auto[0]	217041	1			T32	21		T11	51		T12	52
bins_for_gpio_bits[8]	auto[1]	auto[1]	4801859	1			T32	99		T1	55		T11	163
bins_for_gpio_bits[9]	auto[0]	auto[0]	7308807	1			T32	272		T1	64		T11	596
bins_for_gpio_bits[9]	auto[0]	auto[1]	217375	1			T32	19		T11	50		T12	58
bins_for_gpio_bits[9]	auto[1]	auto[0]	217621	1			T32	19		T11	50		T12	58
bins_for_gpio_bits[9]	auto[1]	auto[1]	4785120	1			T32	77		T1	63		T11	187
bins_for_gpio_bits[10]	auto[0]	auto[0]	7291849	1			T32	246		T1	71		T11	595
bins_for_gpio_bits[10]	auto[0]	auto[1]	217223	1			T32	15		T11	52		T12	48
bins_for_gpio_bits[10]	auto[1]	auto[0]	217477	1			T32	15		T11	53		T12	48
bins_for_gpio_bits[10]	auto[1]	auto[1]	4802374	1			T32	111		T1	56		T11	183
bins_for_gpio_bits[11]	auto[0]	auto[0]	7295355	1			T32	269		T1	61		T11	592
bins_for_gpio_bits[11]	auto[0]	auto[1]	217744	1			T32	17		T11	53		T12	43
bins_for_gpio_bits[11]	auto[1]	auto[0]	217966	1			T32	17		T11	53		T12	43
bins_for_gpio_bits[11]	auto[1]	auto[1]	4797858	1			T32	84		T1	66		T11	185
bins_for_gpio_bits[12]	auto[0]	auto[0]	7294878	1			T32	278		T1	59		T11	571
bins_for_gpio_bits[12]	auto[0]	auto[1]	217318	1			T32	15		T11	49		T12	52
bins_for_gpio_bits[12]	auto[1]	auto[0]	217613	1			T32	15		T11	49		T12	52
bins_for_gpio_bits[12]	auto[1]	auto[1]	4799114	1			T32	79		T1	68		T11	214
bins_for_gpio_bits[13]	auto[0]	auto[0]	7298567	1			T32	246		T1	57		T11	601
bins_for_gpio_bits[13]	auto[0]	auto[1]	217420	1			T32	19		T11	49		T12	46
bins_for_gpio_bits[13]	auto[1]	auto[0]	217678	1			T32	19		T11	49		T12	46
bins_for_gpio_bits[13]	auto[1]	auto[1]	4795258	1			T32	103		T1	70		T11	184
bins_for_gpio_bits[14]	auto[0]	auto[0]	7285700	1			T32	252		T1	82		T11	641
bins_for_gpio_bits[14]	auto[0]	auto[1]	217958	1			T32	23		T11	45		T12	44
bins_for_gpio_bits[14]	auto[1]	auto[0]	218238	1			T32	23		T11	45		T12	44
bins_for_gpio_bits[14]	auto[1]	auto[1]	4807027	1			T32	89		T1	45		T11	152
bins_for_gpio_bits[15]	auto[0]	auto[0]	7294137	1			T32	265		T1	42		T11	564
bins_for_gpio_bits[15]	auto[0]	auto[1]	216903	1			T32	18		T11	47		T12	48
bins_for_gpio_bits[15]	auto[1]	auto[0]	217196	1			T32	18		T11	47		T12	49
bins_for_gpio_bits[15]	auto[1]	auto[1]	4800687	1			T32	86		T1	85		T11	225
bins_for_gpio_bits[16]	auto[0]	auto[0]	7295353	1			T32	242		T1	83		T11	566
bins_for_gpio_bits[16]	auto[0]	auto[1]	217388	1			T32	22		T11	59		T12	46
bins_for_gpio_bits[16]	auto[1]	auto[0]	217664	1			T32	23		T11	59		T12	46
bins_for_gpio_bits[16]	auto[1]	auto[1]	4798518	1			T32	100		T1	44		T11	199
bins_for_gpio_bits[17]	auto[0]	auto[0]	7305276	1			T32	233		T1	95		T11	543
bins_for_gpio_bits[17]	auto[0]	auto[1]	217572	1			T32	22		T11	56		T12	49
bins_for_gpio_bits[17]	auto[1]	auto[0]	217870	1			T32	22		T11	56		T12	49
bins_for_gpio_bits[17]	auto[1]	auto[1]	4788205	1			T32	110		T1	32		T11	228
bins_for_gpio_bits[18]	auto[0]	auto[0]	7305878	1			T32	236		T1	42		T11	610
bins_for_gpio_bits[18]	auto[0]	auto[1]	217362	1			T32	18		T11	48		T12	37
bins_for_gpio_bits[18]	auto[1]	auto[0]	217571	1			T32	18		T11	48		T12	37
bins_for_gpio_bits[18]	auto[1]	auto[1]	4788112	1			T32	115		T1	85		T11	177
bins_for_gpio_bits[19]	auto[0]	auto[0]	7296225	1			T32	268		T1	70		T11	585
bins_for_gpio_bits[19]	auto[0]	auto[1]	217903	1			T32	19		T11	49		T12	50
bins_for_gpio_bits[19]	auto[1]	auto[0]	218147	1			T32	19		T11	49		T12	50
bins_for_gpio_bits[19]	auto[1]	auto[1]	4796648	1			T32	81		T1	57		T11	200
bins_for_gpio_bits[20]	auto[0]	auto[0]	7299614	1			T32	231		T1	73		T11	606
bins_for_gpio_bits[20]	auto[0]	auto[1]	217082	1			T32	23		T11	44		T12	43
bins_for_gpio_bits[20]	auto[1]	auto[0]	217330	1			T32	24		T11	45		T12	44
bins_for_gpio_bits[20]	auto[1]	auto[1]	4794897	1			T32	109		T1	54		T11	188
bins_for_gpio_bits[21]	auto[0]	auto[0]	7299647	1			T32	243		T1	59		T11	600
bins_for_gpio_bits[21]	auto[0]	auto[1]	217839	1			T32	22		T11	49		T12	49
bins_for_gpio_bits[21]	auto[1]	auto[0]	218116	1			T32	22		T11	50		T12	49
bins_for_gpio_bits[21]	auto[1]	auto[1]	4793321	1			T32	100		T1	68		T11	184
bins_for_gpio_bits[22]	auto[0]	auto[0]	7289631	1			T32	216		T1	49		T11	614
bins_for_gpio_bits[22]	auto[0]	auto[1]	217915	1			T32	22		T11	47		T12	42
bins_for_gpio_bits[22]	auto[1]	auto[0]	218198	1			T32	22		T11	47		T12	43
bins_for_gpio_bits[22]	auto[1]	auto[1]	4803179	1			T32	127		T1	78		T11	175
bins_for_gpio_bits[23]	auto[0]	auto[0]	7303188	1			T32	234		T1	77		T11	561
bins_for_gpio_bits[23]	auto[0]	auto[1]	217000	1			T32	22		T11	51		T12	47
bins_for_gpio_bits[23]	auto[1]	auto[0]	217287	1			T32	22		T11	51		T12	47
bins_for_gpio_bits[23]	auto[1]	auto[1]	4791448	1			T32	109		T1	50		T11	220
bins_for_gpio_bits[24]	auto[0]	auto[0]	7296653	1			T32	241		T1	78		T11	602
bins_for_gpio_bits[24]	auto[0]	auto[1]	217006	1			T32	21		T11	52		T12	44
bins_for_gpio_bits[24]	auto[1]	auto[0]	217304	1			T32	22		T11	52		T12	45
bins_for_gpio_bits[24]	auto[1]	auto[1]	4797960	1			T32	103		T1	49		T11	177
bins_for_gpio_bits[25]	auto[0]	auto[0]	7303171	1			T32	226		T1	82		T11	606
bins_for_gpio_bits[25]	auto[0]	auto[1]	217411	1			T32	23		T11	51		T12	47
bins_for_gpio_bits[25]	auto[1]	auto[0]	217690	1			T32	24		T11	52		T12	47
bins_for_gpio_bits[25]	auto[1]	auto[1]	4790651	1			T32	114		T1	45		T11	174
bins_for_gpio_bits[26]	auto[0]	auto[0]	7299028	1			T32	270		T1	60		T11	582
bins_for_gpio_bits[26]	auto[0]	auto[1]	216865	1			T32	16		T11	47		T12	51
bins_for_gpio_bits[26]	auto[1]	auto[0]	217096	1			T32	16		T11	47		T12	51
bins_for_gpio_bits[26]	auto[1]	auto[1]	4795934	1			T32	85		T1	67		T11	207
bins_for_gpio_bits[27]	auto[0]	auto[0]	7304650	1			T32	248		T1	67		T11	584
bins_for_gpio_bits[27]	auto[0]	auto[1]	217185	1			T32	19		T11	45		T12	45
bins_for_gpio_bits[27]	auto[1]	auto[0]	217473	1			T32	20		T11	46		T12	45
bins_for_gpio_bits[27]	auto[1]	auto[1]	4789615	1			T32	100		T1	60		T11	208
bins_for_gpio_bits[28]	auto[0]	auto[0]	7298509	1			T32	228		T1	51		T11	578
bins_for_gpio_bits[28]	auto[0]	auto[1]	217771	1			T32	22		T11	47		T12	37
bins_for_gpio_bits[28]	auto[1]	auto[0]	218069	1			T32	22		T11	48		T12	37
bins_for_gpio_bits[28]	auto[1]	auto[1]	4794574	1			T32	115		T1	76		T11	210
bins_for_gpio_bits[29]	auto[0]	auto[0]	7290611	1			T32	257		T1	73		T11	540
bins_for_gpio_bits[29]	auto[0]	auto[1]	217064	1			T32	18		T11	57		T12	46
bins_for_gpio_bits[29]	auto[1]	auto[0]	217352	1			T32	18		T11	57		T12	46
bins_for_gpio_bits[29]	auto[1]	auto[1]	4803896	1			T32	94		T1	54		T11	229
bins_for_gpio_bits[30]	auto[0]	auto[0]	7297987	1			T32	260		T1	59		T11	633
bins_for_gpio_bits[30]	auto[0]	auto[1]	216870	1			T32	12		T11	44		T12	50
bins_for_gpio_bits[30]	auto[1]	auto[0]	217181	1			T32	13		T11	44		T12	50
bins_for_gpio_bits[30]	auto[1]	auto[1]	4796885	1			T32	102		T1	68		T11	162
bins_for_gpio_bits[31]	auto[0]	auto[0]	7297807	1			T32	245		T1	94		T11	561
bins_for_gpio_bits[31]	auto[0]	auto[1]	217741	1			T32	16		T11	51		T12	53
bins_for_gpio_bits[31]	auto[1]	auto[0]	218036	1			T32	17		T11	52		T12	54
bins_for_gpio_bits[31]	auto[1]	auto[1]	4795339	1			T32	109		T1	33		T11	219