Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445725 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5270924 |
1 |
|
|
T1 |
17 |
|
T14 |
26 |
|
T16 |
22073 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12045485 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
671164 |
1 |
|
|
T14 |
1 |
|
T16 |
2574 |
|
T112 |
93 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7422060 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5294589 |
1 |
|
|
T1 |
6 |
|
T14 |
15 |
|
T16 |
21136 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2313439 |
1 |
|
|
T1 |
6 |
|
T14 |
4 |
|
T16 |
8981 |
| auto[1] |
auto[0] |
auto[1] |
336741 |
1 |
|
|
T16 |
1329 |
|
T112 |
61 |
|
T22 |
133 |
| auto[1] |
auto[1] |
auto[0] |
2309986 |
1 |
|
|
T14 |
10 |
|
T16 |
9581 |
|
T112 |
137 |
| auto[1] |
auto[1] |
auto[1] |
334423 |
1 |
|
|
T14 |
1 |
|
T16 |
1245 |
|
T112 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462428 |
1 |
|
|
T32 |
231 |
|
T1 |
29 |
|
T11 |
483 |
| auto[1] |
5254221 |
1 |
|
|
T1 |
30 |
|
T14 |
25 |
|
T16 |
20526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047756 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668893 |
1 |
|
|
T14 |
2 |
|
T16 |
2633 |
|
T112 |
119 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431201 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5285448 |
1 |
|
|
T1 |
5 |
|
T14 |
19 |
|
T16 |
21634 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2315625 |
1 |
|
|
T14 |
11 |
|
T16 |
10232 |
|
T112 |
234 |
| auto[1] |
auto[0] |
auto[1] |
335574 |
1 |
|
|
T14 |
2 |
|
T16 |
1438 |
|
T112 |
55 |
| auto[1] |
auto[1] |
auto[0] |
2300930 |
1 |
|
|
T1 |
5 |
|
T14 |
6 |
|
T16 |
8769 |
| auto[1] |
auto[1] |
auto[1] |
333319 |
1 |
|
|
T16 |
1195 |
|
T112 |
64 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441776 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5274873 |
1 |
|
|
T1 |
17 |
|
T14 |
26 |
|
T16 |
21257 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047396 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669253 |
1 |
|
|
T14 |
1 |
|
T16 |
2744 |
|
T112 |
104 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434468 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5282181 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T16 |
22194 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2310787 |
1 |
|
|
T1 |
6 |
|
T14 |
3 |
|
T16 |
10048 |
| auto[1] |
auto[0] |
auto[1] |
334595 |
1 |
|
|
T14 |
1 |
|
T16 |
1420 |
|
T112 |
67 |
| auto[1] |
auto[1] |
auto[0] |
2302141 |
1 |
|
|
T14 |
2 |
|
T16 |
9402 |
|
T112 |
169 |
| auto[1] |
auto[1] |
auto[1] |
334658 |
1 |
|
|
T16 |
1324 |
|
T112 |
37 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7415871 |
1 |
|
|
T32 |
231 |
|
T1 |
43 |
|
T11 |
483 |
| auto[1] |
5300778 |
1 |
|
|
T1 |
16 |
|
T14 |
16 |
|
T16 |
21378 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12052616 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
664033 |
1 |
|
|
T14 |
1 |
|
T16 |
2568 |
|
T112 |
90 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468714 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5247935 |
1 |
|
|
T1 |
6 |
|
T14 |
8 |
|
T16 |
20902 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2279221 |
1 |
|
|
T1 |
6 |
|
T14 |
7 |
|
T16 |
8981 |
| auto[1] |
auto[0] |
auto[1] |
330140 |
1 |
|
|
T14 |
1 |
|
T16 |
1343 |
|
T112 |
42 |
| auto[1] |
auto[1] |
auto[0] |
2304681 |
1 |
|
|
T16 |
9353 |
|
T112 |
210 |
|
T2 |
172 |
| auto[1] |
auto[1] |
auto[1] |
333893 |
1 |
|
|
T16 |
1225 |
|
T112 |
48 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460895 |
1 |
|
|
T32 |
231 |
|
T1 |
44 |
|
T11 |
483 |
| auto[1] |
5255754 |
1 |
|
|
T1 |
15 |
|
T14 |
27 |
|
T16 |
21098 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047553 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669096 |
1 |
|
|
T16 |
2619 |
|
T112 |
78 |
|
T2 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435120 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5281529 |
1 |
|
|
T1 |
11 |
|
T14 |
4 |
|
T16 |
21016 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2307045 |
1 |
|
|
T1 |
11 |
|
T16 |
9535 |
|
T112 |
118 |
| auto[1] |
auto[0] |
auto[1] |
334777 |
1 |
|
|
T16 |
1414 |
|
T112 |
24 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2305388 |
1 |
|
|
T14 |
4 |
|
T16 |
8862 |
|
T112 |
247 |
| auto[1] |
auto[1] |
auto[1] |
334319 |
1 |
|
|
T16 |
1205 |
|
T112 |
54 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439147 |
1 |
|
|
T32 |
231 |
|
T1 |
37 |
|
T11 |
483 |
| auto[1] |
5277502 |
1 |
|
|
T1 |
22 |
|
T14 |
21 |
|
T16 |
22022 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12051001 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
665648 |
1 |
|
|
T16 |
2473 |
|
T112 |
52 |
|
T2 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459637 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5257012 |
1 |
|
|
T1 |
6 |
|
T16 |
19787 |
|
T112 |
308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2303108 |
1 |
|
|
T1 |
6 |
|
T16 |
8856 |
|
T112 |
187 |
| auto[1] |
auto[0] |
auto[1] |
333828 |
1 |
|
|
T16 |
1283 |
|
T112 |
36 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2288256 |
1 |
|
|
T16 |
8458 |
|
T112 |
69 |
|
T2 |
225 |
| auto[1] |
auto[1] |
auto[1] |
331820 |
1 |
|
|
T16 |
1190 |
|
T112 |
16 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423988 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5292661 |
1 |
|
|
T1 |
6 |
|
T14 |
29 |
|
T16 |
21413 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12053453 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
663196 |
1 |
|
|
T16 |
2596 |
|
T112 |
86 |
|
T2 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468671 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5247978 |
1 |
|
|
T1 |
6 |
|
T14 |
2 |
|
T16 |
21802 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2295411 |
1 |
|
|
T1 |
6 |
|
T16 |
9158 |
|
T112 |
226 |
| auto[1] |
auto[0] |
auto[1] |
332738 |
1 |
|
|
T16 |
1205 |
|
T112 |
49 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2289371 |
1 |
|
|
T14 |
2 |
|
T16 |
10048 |
|
T112 |
207 |
| auto[1] |
auto[1] |
auto[1] |
330458 |
1 |
|
|
T16 |
1391 |
|
T112 |
37 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424261 |
1 |
|
|
T32 |
231 |
|
T1 |
36 |
|
T11 |
483 |
| auto[1] |
5292388 |
1 |
|
|
T1 |
23 |
|
T14 |
17 |
|
T16 |
21361 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047383 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669266 |
1 |
|
|
T16 |
2747 |
|
T112 |
82 |
|
T2 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7429969 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5286680 |
1 |
|
|
T1 |
5 |
|
T14 |
17 |
|
T16 |
22126 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2306896 |
1 |
|
|
T14 |
12 |
|
T16 |
10026 |
|
T112 |
279 |
| auto[1] |
auto[0] |
auto[1] |
333778 |
1 |
|
|
T16 |
1477 |
|
T112 |
71 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2310518 |
1 |
|
|
T1 |
5 |
|
T14 |
5 |
|
T16 |
9353 |
| auto[1] |
auto[1] |
auto[1] |
335488 |
1 |
|
|
T16 |
1270 |
|
T112 |
11 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424940 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5291709 |
1 |
|
|
T1 |
17 |
|
T14 |
23 |
|
T16 |
21159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12044394 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
672255 |
1 |
|
|
T14 |
1 |
|
T16 |
2585 |
|
T112 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7418703 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5297946 |
1 |
|
|
T1 |
11 |
|
T14 |
10 |
|
T16 |
21322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2311586 |
1 |
|
|
T1 |
11 |
|
T14 |
7 |
|
T16 |
9892 |
| auto[1] |
auto[0] |
auto[1] |
335607 |
1 |
|
|
T14 |
1 |
|
T16 |
1398 |
|
T112 |
32 |
| auto[1] |
auto[1] |
auto[0] |
2314105 |
1 |
|
|
T14 |
2 |
|
T16 |
8845 |
|
T112 |
133 |
| auto[1] |
auto[1] |
auto[1] |
336648 |
1 |
|
|
T16 |
1187 |
|
T112 |
33 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441324 |
1 |
|
|
T32 |
231 |
|
T1 |
31 |
|
T11 |
483 |
| auto[1] |
5275325 |
1 |
|
|
T1 |
28 |
|
T14 |
23 |
|
T16 |
21625 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047781 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668868 |
1 |
|
|
T14 |
1 |
|
T16 |
2749 |
|
T112 |
111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431359 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5285290 |
1 |
|
|
T1 |
6 |
|
T14 |
15 |
|
T16 |
21848 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2310028 |
1 |
|
|
T14 |
14 |
|
T16 |
9552 |
|
T112 |
234 |
| auto[1] |
auto[0] |
auto[1] |
334951 |
1 |
|
|
T14 |
1 |
|
T16 |
1352 |
|
T112 |
64 |
| auto[1] |
auto[1] |
auto[0] |
2306394 |
1 |
|
|
T1 |
6 |
|
T16 |
9547 |
|
T112 |
184 |
| auto[1] |
auto[1] |
auto[1] |
333917 |
1 |
|
|
T16 |
1397 |
|
T112 |
47 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453491 |
1 |
|
|
T32 |
231 |
|
T1 |
19 |
|
T11 |
483 |
| auto[1] |
5263158 |
1 |
|
|
T1 |
40 |
|
T14 |
33 |
|
T16 |
23078 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047806 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668843 |
1 |
|
|
T16 |
2554 |
|
T112 |
81 |
|
T2 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442563 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5274086 |
1 |
|
|
T14 |
6 |
|
T16 |
20904 |
|
T112 |
431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2308586 |
1 |
|
|
T14 |
4 |
|
T16 |
8926 |
|
T112 |
156 |
| auto[1] |
auto[0] |
auto[1] |
335600 |
1 |
|
|
T16 |
1181 |
|
T112 |
38 |
|
T2 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2296657 |
1 |
|
|
T14 |
2 |
|
T16 |
9424 |
|
T112 |
194 |
| auto[1] |
auto[1] |
auto[1] |
333243 |
1 |
|
|
T16 |
1373 |
|
T112 |
43 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453202 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5263447 |
1 |
|
|
T1 |
6 |
|
T14 |
24 |
|
T16 |
21091 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046724 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669925 |
1 |
|
|
T14 |
2 |
|
T16 |
2819 |
|
T112 |
92 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423430 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5293219 |
1 |
|
|
T1 |
5 |
|
T14 |
19 |
|
T16 |
22812 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324256 |
1 |
|
|
T1 |
5 |
|
T14 |
12 |
|
T16 |
10020 |
| auto[1] |
auto[0] |
auto[1] |
337132 |
1 |
|
|
T14 |
1 |
|
T16 |
1411 |
|
T112 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2299038 |
1 |
|
|
T14 |
5 |
|
T16 |
9973 |
|
T112 |
329 |
| auto[1] |
auto[1] |
auto[1] |
332793 |
1 |
|
|
T14 |
1 |
|
T16 |
1408 |
|
T112 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456100 |
1 |
|
|
T32 |
231 |
|
T1 |
40 |
|
T11 |
483 |
| auto[1] |
5260549 |
1 |
|
|
T1 |
19 |
|
T14 |
23 |
|
T16 |
22353 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12052871 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
663778 |
1 |
|
|
T14 |
1 |
|
T16 |
2728 |
|
T112 |
93 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471741 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5244908 |
1 |
|
|
T1 |
5 |
|
T14 |
19 |
|
T16 |
21994 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2295175 |
1 |
|
|
T1 |
5 |
|
T14 |
6 |
|
T16 |
9291 |
| auto[1] |
auto[0] |
auto[1] |
332241 |
1 |
|
|
T16 |
1305 |
|
T112 |
42 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2285955 |
1 |
|
|
T14 |
12 |
|
T16 |
9975 |
|
T112 |
206 |
| auto[1] |
auto[1] |
auto[1] |
331537 |
1 |
|
|
T14 |
1 |
|
T16 |
1423 |
|
T112 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7397026 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5319623 |
1 |
|
|
T1 |
17 |
|
T14 |
37 |
|
T16 |
21077 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047309 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669340 |
1 |
|
|
T14 |
2 |
|
T16 |
2593 |
|
T112 |
112 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424727 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5291922 |
1 |
|
|
T1 |
5 |
|
T14 |
14 |
|
T16 |
21125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2301113 |
1 |
|
|
T1 |
5 |
|
T14 |
4 |
|
T16 |
9454 |
| auto[1] |
auto[0] |
auto[1] |
332412 |
1 |
|
|
T16 |
1357 |
|
T112 |
39 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2321469 |
1 |
|
|
T14 |
8 |
|
T16 |
9078 |
|
T112 |
299 |
| auto[1] |
auto[1] |
auto[1] |
336928 |
1 |
|
|
T14 |
2 |
|
T16 |
1236 |
|
T112 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7444177 |
1 |
|
|
T32 |
231 |
|
T1 |
35 |
|
T11 |
483 |
| auto[1] |
5272472 |
1 |
|
|
T1 |
24 |
|
T14 |
9 |
|
T16 |
19977 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12051981 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
664668 |
1 |
|
|
T14 |
1 |
|
T16 |
2628 |
|
T112 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7467056 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5249593 |
1 |
|
|
T14 |
16 |
|
T16 |
21001 |
|
T112 |
568 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2278565 |
1 |
|
|
T14 |
15 |
|
T16 |
10089 |
|
T112 |
272 |
| auto[1] |
auto[0] |
auto[1] |
328841 |
1 |
|
|
T14 |
1 |
|
T16 |
1453 |
|
T112 |
65 |
| auto[1] |
auto[1] |
auto[0] |
2306360 |
1 |
|
|
T16 |
8284 |
|
T112 |
183 |
|
T2 |
261 |
| auto[1] |
auto[1] |
auto[1] |
335827 |
1 |
|
|
T16 |
1175 |
|
T112 |
48 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449325 |
1 |
|
|
T32 |
231 |
|
T1 |
36 |
|
T11 |
483 |
| auto[1] |
5267324 |
1 |
|
|
T1 |
23 |
|
T14 |
22 |
|
T16 |
21947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12048432 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668217 |
1 |
|
|
T16 |
2510 |
|
T112 |
62 |
|
T2 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439186 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5277463 |
1 |
|
|
T14 |
11 |
|
T16 |
20750 |
|
T112 |
339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2310772 |
1 |
|
|
T14 |
7 |
|
T16 |
8900 |
|
T112 |
205 |
| auto[1] |
auto[0] |
auto[1] |
336586 |
1 |
|
|
T16 |
1157 |
|
T112 |
45 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2298474 |
1 |
|
|
T14 |
4 |
|
T16 |
9340 |
|
T112 |
72 |
| auto[1] |
auto[1] |
auto[1] |
331631 |
1 |
|
|
T16 |
1353 |
|
T112 |
17 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466789 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5249860 |
1 |
|
|
T1 |
17 |
|
T14 |
23 |
|
T16 |
22867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046928 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669721 |
1 |
|
|
T16 |
2668 |
|
T112 |
127 |
|
T2 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7429251 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5287398 |
1 |
|
|
T1 |
11 |
|
T14 |
19 |
|
T16 |
21177 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2314792 |
1 |
|
|
T1 |
11 |
|
T14 |
17 |
|
T16 |
8736 |
| auto[1] |
auto[0] |
auto[1] |
336595 |
1 |
|
|
T16 |
1198 |
|
T112 |
77 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2302885 |
1 |
|
|
T14 |
2 |
|
T16 |
9773 |
|
T112 |
183 |
| auto[1] |
auto[1] |
auto[1] |
333126 |
1 |
|
|
T16 |
1470 |
|
T112 |
50 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426484 |
1 |
|
|
T32 |
231 |
|
T1 |
37 |
|
T11 |
483 |
| auto[1] |
5290165 |
1 |
|
|
T1 |
22 |
|
T14 |
23 |
|
T16 |
20655 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12047978 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668671 |
1 |
|
|
T16 |
2506 |
|
T112 |
67 |
|
T2 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7442922 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5273727 |
1 |
|
|
T1 |
6 |
|
T14 |
21 |
|
T16 |
20494 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2307424 |
1 |
|
|
T14 |
17 |
|
T16 |
9353 |
|
T112 |
121 |
| auto[1] |
auto[0] |
auto[1] |
335722 |
1 |
|
|
T16 |
1307 |
|
T112 |
29 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2297632 |
1 |
|
|
T1 |
6 |
|
T14 |
4 |
|
T16 |
8635 |
| auto[1] |
auto[1] |
auto[1] |
332949 |
1 |
|
|
T16 |
1199 |
|
T112 |
38 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7449096 |
1 |
|
|
T32 |
231 |
|
T1 |
25 |
|
T11 |
483 |
| auto[1] |
5267553 |
1 |
|
|
T1 |
34 |
|
T14 |
14 |
|
T16 |
21861 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12049102 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
667547 |
1 |
|
|
T16 |
2608 |
|
T112 |
100 |
|
T2 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7444842 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5271807 |
1 |
|
|
T14 |
6 |
|
T16 |
20509 |
|
T112 |
496 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2312698 |
1 |
|
|
T14 |
6 |
|
T16 |
8715 |
|
T112 |
163 |
| auto[1] |
auto[0] |
auto[1] |
335646 |
1 |
|
|
T16 |
1291 |
|
T112 |
41 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2291562 |
1 |
|
|
T16 |
9186 |
|
T112 |
233 |
|
T2 |
68 |
| auto[1] |
auto[1] |
auto[1] |
331901 |
1 |
|
|
T16 |
1317 |
|
T112 |
59 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434645 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5282004 |
1 |
|
|
T1 |
6 |
|
T14 |
9 |
|
T16 |
20875 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046032 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
670617 |
1 |
|
|
T14 |
1 |
|
T16 |
2639 |
|
T112 |
126 |