Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447564 |
1 |
|
|
T32 |
231 |
|
T1 |
41 |
|
T11 |
483 |
| auto[1] |
5269085 |
1 |
|
|
T1 |
18 |
|
T14 |
35 |
|
T16 |
21795 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12049617 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
667032 |
1 |
|
|
T14 |
1 |
|
T16 |
2733 |
|
T112 |
52 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443211 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5273438 |
1 |
|
|
T14 |
9 |
|
T16 |
21581 |
|
T112 |
291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2307715 |
1 |
|
|
T16 |
9203 |
|
T112 |
87 |
|
T2 |
168 |
| auto[1] |
auto[0] |
auto[1] |
334603 |
1 |
|
|
T16 |
1348 |
|
T112 |
19 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2298691 |
1 |
|
|
T14 |
8 |
|
T16 |
9645 |
|
T112 |
152 |
| auto[1] |
auto[1] |
auto[1] |
332429 |
1 |
|
|
T14 |
1 |
|
T16 |
1385 |
|
T112 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |