Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440168 |
1 |
|
|
T32 |
231 |
|
T1 |
37 |
|
T11 |
483 |
| auto[1] |
5276481 |
1 |
|
|
T1 |
22 |
|
T14 |
15 |
|
T16 |
21434 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12046981 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
669668 |
1 |
|
|
T14 |
1 |
|
T16 |
2608 |
|
T112 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435231 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
5281418 |
1 |
|
|
T1 |
5 |
|
T14 |
15 |
|
T16 |
22025 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2314032 |
1 |
|
|
T1 |
5 |
|
T14 |
9 |
|
T16 |
9875 |
| auto[1] |
auto[0] |
auto[1] |
335608 |
1 |
|
|
T14 |
1 |
|
T16 |
1366 |
|
T112 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2297718 |
1 |
|
|
T14 |
5 |
|
T16 |
9542 |
|
T112 |
284 |
| auto[1] |
auto[1] |
auto[1] |
334060 |
1 |
|
|
T16 |
1242 |
|
T112 |
66 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |