Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7430240 |
1 |
|
|
T32 |
231 |
|
T1 |
38 |
|
T11 |
483 |
| auto[1] |
5286409 |
1 |
|
|
T1 |
21 |
|
T14 |
12 |
|
T16 |
21490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12049180 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
667469 |
1 |
|
|
T14 |
1 |
|
T16 |
2751 |
|
T112 |
100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447898 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
5268751 |
1 |
|
|
T14 |
16 |
|
T16 |
21949 |
|
T112 |
497 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2292206 |
1 |
|
|
T14 |
15 |
|
T16 |
9519 |
|
T112 |
221 |
| auto[1] |
auto[0] |
auto[1] |
332153 |
1 |
|
|
T14 |
1 |
|
T16 |
1330 |
|
T112 |
58 |
| auto[1] |
auto[1] |
auto[0] |
2309076 |
1 |
|
|
T16 |
9679 |
|
T112 |
176 |
|
T2 |
154 |
| auto[1] |
auto[1] |
auto[1] |
335316 |
1 |
|
|
T16 |
1421 |
|
T112 |
42 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |