Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431011 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5285638 |
1 |
|
|
T1 |
11 |
|
T14 |
23 |
|
T16 |
20767 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12048662 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
667987 |
1 |
|
|
T16 |
2691 |
|
T112 |
79 |
|
T2 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7448636 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5268013 |
1 |
|
|
T1 |
6 |
|
T14 |
14 |
|
T16 |
21622 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2298077 |
1 |
|
|
T14 |
10 |
|
T16 |
10002 |
|
T112 |
134 |
| auto[1] |
auto[0] |
auto[1] |
333017 |
1 |
|
|
T16 |
1485 |
|
T112 |
29 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2301949 |
1 |
|
|
T1 |
6 |
|
T14 |
4 |
|
T16 |
8929 |
| auto[1] |
auto[1] |
auto[1] |
334970 |
1 |
|
|
T16 |
1206 |
|
T112 |
50 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |