Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445725 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5270924 |
1 |
|
|
T1 |
17 |
|
T14 |
26 |
|
T16 |
22073 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10563933 |
1 |
|
|
T32 |
231 |
|
T1 |
56 |
|
T11 |
483 |
| auto[1] |
2152716 |
1 |
|
|
T1 |
3 |
|
T14 |
4 |
|
T16 |
13323 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440902 |
1 |
|
|
T32 |
231 |
|
T1 |
50 |
|
T11 |
483 |
| auto[1] |
5275747 |
1 |
|
|
T1 |
9 |
|
T14 |
16 |
|
T16 |
21809 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1558140 |
1 |
|
|
T1 |
6 |
|
T14 |
11 |
|
T16 |
4153 |
| auto[1] |
auto[0] |
auto[1] |
1073431 |
1 |
|
|
T1 |
3 |
|
T14 |
2 |
|
T16 |
6407 |
| auto[1] |
auto[1] |
auto[0] |
1564891 |
1 |
|
|
T14 |
1 |
|
T16 |
4333 |
|
T112 |
154 |
| auto[1] |
auto[1] |
auto[1] |
1079285 |
1 |
|
|
T14 |
2 |
|
T16 |
6916 |
|
T112 |
163 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |