Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462428 |
1 |
|
|
T32 |
231 |
|
T1 |
29 |
|
T11 |
483 |
| auto[1] |
5254221 |
1 |
|
|
T1 |
30 |
|
T14 |
25 |
|
T16 |
20526 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10561917 |
1 |
|
|
T32 |
231 |
|
T1 |
51 |
|
T11 |
483 |
| auto[1] |
2154732 |
1 |
|
|
T1 |
8 |
|
T14 |
8 |
|
T16 |
12189 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7438374 |
1 |
|
|
T32 |
231 |
|
T1 |
40 |
|
T11 |
483 |
| auto[1] |
5278275 |
1 |
|
|
T1 |
19 |
|
T14 |
15 |
|
T16 |
20178 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1574632 |
1 |
|
|
T1 |
1 |
|
T14 |
5 |
|
T16 |
4331 |
| auto[1] |
auto[0] |
auto[1] |
1086262 |
1 |
|
|
T14 |
8 |
|
T16 |
6463 |
|
T112 |
144 |
| auto[1] |
auto[1] |
auto[0] |
1548911 |
1 |
|
|
T1 |
10 |
|
T14 |
2 |
|
T16 |
3658 |
| auto[1] |
auto[1] |
auto[1] |
1068470 |
1 |
|
|
T1 |
8 |
|
T16 |
5726 |
|
T112 |
105 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |