Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7415871 |
1 |
|
|
T32 |
231 |
|
T1 |
43 |
|
T11 |
483 |
| auto[1] |
5300778 |
1 |
|
|
T1 |
16 |
|
T14 |
16 |
|
T16 |
21378 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558320 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
2158329 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T16 |
13101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431149 |
1 |
|
|
T32 |
231 |
|
T1 |
52 |
|
T11 |
483 |
| auto[1] |
5285500 |
1 |
|
|
T1 |
7 |
|
T14 |
15 |
|
T16 |
21863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1562974 |
1 |
|
|
T1 |
1 |
|
T14 |
9 |
|
T16 |
4958 |
| auto[1] |
auto[0] |
auto[1] |
1078294 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T16 |
6732 |
| auto[1] |
auto[1] |
auto[0] |
1564197 |
1 |
|
|
T16 |
3804 |
|
T112 |
116 |
|
T2 |
122 |
| auto[1] |
auto[1] |
auto[1] |
1080035 |
1 |
|
|
T16 |
6369 |
|
T112 |
128 |
|
T2 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |