Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460895 |
1 |
|
|
T32 |
231 |
|
T1 |
44 |
|
T11 |
483 |
| auto[1] |
5255754 |
1 |
|
|
T1 |
15 |
|
T14 |
27 |
|
T16 |
21098 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10574614 |
1 |
|
|
T32 |
231 |
|
T1 |
58 |
|
T11 |
483 |
| auto[1] |
2142035 |
1 |
|
|
T1 |
1 |
|
T14 |
9 |
|
T16 |
13155 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7470372 |
1 |
|
|
T32 |
231 |
|
T1 |
58 |
|
T11 |
483 |
| auto[1] |
5246277 |
1 |
|
|
T1 |
1 |
|
T14 |
18 |
|
T16 |
21607 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1566168 |
1 |
|
|
T14 |
4 |
|
T16 |
4555 |
|
T112 |
52 |
| auto[1] |
auto[0] |
auto[1] |
1077230 |
1 |
|
|
T1 |
1 |
|
T14 |
4 |
|
T16 |
6896 |
| auto[1] |
auto[1] |
auto[0] |
1538074 |
1 |
|
|
T14 |
5 |
|
T16 |
3897 |
|
T112 |
70 |
| auto[1] |
auto[1] |
auto[1] |
1064805 |
1 |
|
|
T14 |
5 |
|
T16 |
6259 |
|
T112 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |