Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423988 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5292661 |
1 |
|
|
T1 |
6 |
|
T14 |
29 |
|
T16 |
21413 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10569038 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
2147611 |
1 |
|
|
T1 |
17 |
|
T14 |
4 |
|
T16 |
12510 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460837 |
1 |
|
|
T32 |
231 |
|
T1 |
38 |
|
T11 |
483 |
| auto[1] |
5255812 |
1 |
|
|
T1 |
21 |
|
T14 |
10 |
|
T16 |
21110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1551355 |
1 |
|
|
T1 |
4 |
|
T14 |
3 |
|
T16 |
4391 |
| auto[1] |
auto[0] |
auto[1] |
1073673 |
1 |
|
|
T1 |
14 |
|
T14 |
4 |
|
T16 |
6401 |
| auto[1] |
auto[1] |
auto[0] |
1556846 |
1 |
|
|
T14 |
3 |
|
T16 |
4209 |
|
T112 |
62 |
| auto[1] |
auto[1] |
auto[1] |
1073938 |
1 |
|
|
T1 |
3 |
|
T16 |
6109 |
|
T112 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |