Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7424261 |
1 |
|
|
T32 |
231 |
|
T1 |
36 |
|
T11 |
483 |
| auto[1] |
5292388 |
1 |
|
|
T1 |
23 |
|
T14 |
17 |
|
T16 |
21361 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10572729 |
1 |
|
|
T32 |
231 |
|
T1 |
56 |
|
T11 |
483 |
| auto[1] |
2143920 |
1 |
|
|
T1 |
3 |
|
T14 |
2 |
|
T16 |
12824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7478611 |
1 |
|
|
T32 |
231 |
|
T1 |
56 |
|
T11 |
483 |
| auto[1] |
5238038 |
1 |
|
|
T1 |
3 |
|
T14 |
9 |
|
T16 |
20935 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1536802 |
1 |
|
|
T14 |
7 |
|
T16 |
4303 |
|
T112 |
230 |
| auto[1] |
auto[0] |
auto[1] |
1069769 |
1 |
|
|
T1 |
3 |
|
T14 |
2 |
|
T16 |
6586 |
| auto[1] |
auto[1] |
auto[0] |
1557316 |
1 |
|
|
T16 |
3808 |
|
T112 |
67 |
|
T2 |
208 |
| auto[1] |
auto[1] |
auto[1] |
1074151 |
1 |
|
|
T16 |
6238 |
|
T112 |
67 |
|
T2 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |