Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453491 |
1 |
|
|
T32 |
231 |
|
T1 |
19 |
|
T11 |
483 |
| auto[1] |
5263158 |
1 |
|
|
T1 |
40 |
|
T14 |
33 |
|
T16 |
23078 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10579756 |
1 |
|
|
T32 |
231 |
|
T1 |
56 |
|
T11 |
483 |
| auto[1] |
2136893 |
1 |
|
|
T1 |
3 |
|
T14 |
4 |
|
T16 |
12862 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7477986 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5238663 |
1 |
|
|
T1 |
6 |
|
T14 |
8 |
|
T16 |
21256 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1558086 |
1 |
|
|
T14 |
3 |
|
T16 |
4009 |
|
T112 |
164 |
| auto[1] |
auto[0] |
auto[1] |
1076152 |
1 |
|
|
T14 |
1 |
|
T16 |
6150 |
|
T112 |
168 |
| auto[1] |
auto[1] |
auto[0] |
1543684 |
1 |
|
|
T1 |
3 |
|
T14 |
1 |
|
T16 |
4385 |
| auto[1] |
auto[1] |
auto[1] |
1060741 |
1 |
|
|
T1 |
3 |
|
T14 |
3 |
|
T16 |
6712 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |