Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7397026 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5319623 |
1 |
|
|
T1 |
17 |
|
T14 |
37 |
|
T16 |
21077 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10563568 |
1 |
|
|
T32 |
231 |
|
T1 |
49 |
|
T11 |
483 |
| auto[1] |
2153081 |
1 |
|
|
T1 |
10 |
|
T14 |
2 |
|
T16 |
13200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7436749 |
1 |
|
|
T32 |
231 |
|
T1 |
43 |
|
T11 |
483 |
| auto[1] |
5279900 |
1 |
|
|
T1 |
16 |
|
T14 |
13 |
|
T16 |
21728 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1547458 |
1 |
|
|
T1 |
6 |
|
T14 |
3 |
|
T16 |
4274 |
| auto[1] |
auto[0] |
auto[1] |
1073809 |
1 |
|
|
T1 |
7 |
|
T14 |
2 |
|
T16 |
6398 |
| auto[1] |
auto[1] |
auto[0] |
1579361 |
1 |
|
|
T14 |
8 |
|
T16 |
4254 |
|
T112 |
212 |
| auto[1] |
auto[1] |
auto[1] |
1079272 |
1 |
|
|
T1 |
3 |
|
T16 |
6802 |
|
T112 |
188 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |