Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7444177 |
1 |
|
|
T32 |
231 |
|
T1 |
35 |
|
T11 |
483 |
| auto[1] |
5272472 |
1 |
|
|
T1 |
24 |
|
T14 |
9 |
|
T16 |
19977 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10565642 |
1 |
|
|
T32 |
231 |
|
T1 |
54 |
|
T11 |
483 |
| auto[1] |
2151007 |
1 |
|
|
T1 |
5 |
|
T14 |
7 |
|
T16 |
12309 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455130 |
1 |
|
|
T32 |
231 |
|
T1 |
40 |
|
T11 |
483 |
| auto[1] |
5261519 |
1 |
|
|
T1 |
19 |
|
T14 |
12 |
|
T16 |
20677 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1558533 |
1 |
|
|
T1 |
9 |
|
T14 |
5 |
|
T16 |
4496 |
| auto[1] |
auto[0] |
auto[1] |
1079738 |
1 |
|
|
T1 |
1 |
|
T14 |
4 |
|
T16 |
6334 |
| auto[1] |
auto[1] |
auto[0] |
1551979 |
1 |
|
|
T1 |
5 |
|
T16 |
3872 |
|
T112 |
125 |
| auto[1] |
auto[1] |
auto[1] |
1071269 |
1 |
|
|
T1 |
4 |
|
T14 |
3 |
|
T16 |
5975 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |