Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7476405 |
1 |
|
|
T32 |
231 |
|
T1 |
32 |
|
T11 |
483 |
| auto[1] |
5240244 |
1 |
|
|
T1 |
27 |
|
T14 |
11 |
|
T16 |
22724 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12045558 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
671091 |
1 |
|
|
T16 |
2507 |
|
T112 |
122 |
|
T2 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7417811 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5298838 |
1 |
|
|
T1 |
11 |
|
T14 |
6 |
|
T16 |
20517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2342036 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T16 |
8425 |
| auto[1] |
auto[0] |
auto[1] |
340285 |
1 |
|
|
T16 |
1127 |
|
T112 |
99 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2285711 |
1 |
|
|
T1 |
5 |
|
T16 |
9585 |
|
T112 |
89 |
| auto[1] |
auto[1] |
auto[1] |
330806 |
1 |
|
|
T16 |
1380 |
|
T112 |
23 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |