Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7466789 |
1 |
|
|
T32 |
231 |
|
T1 |
42 |
|
T11 |
483 |
| auto[1] |
5249860 |
1 |
|
|
T1 |
17 |
|
T14 |
23 |
|
T16 |
22867 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10561948 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
2154701 |
1 |
|
|
T14 |
10 |
|
T16 |
13695 |
|
T112 |
210 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447546 |
1 |
|
|
T32 |
231 |
|
T1 |
56 |
|
T11 |
483 |
| auto[1] |
5269103 |
1 |
|
|
T1 |
3 |
|
T14 |
12 |
|
T16 |
22551 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1553458 |
1 |
|
|
T14 |
1 |
|
T16 |
4245 |
|
T112 |
163 |
| auto[1] |
auto[0] |
auto[1] |
1080161 |
1 |
|
|
T14 |
5 |
|
T16 |
6389 |
|
T112 |
108 |
| auto[1] |
auto[1] |
auto[0] |
1560944 |
1 |
|
|
T1 |
3 |
|
T14 |
1 |
|
T16 |
4611 |
| auto[1] |
auto[1] |
auto[1] |
1074540 |
1 |
|
|
T14 |
5 |
|
T16 |
7306 |
|
T112 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |