Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425226 |
1 |
|
|
T32 |
231 |
|
T1 |
25 |
|
T11 |
483 |
| auto[1] |
5291423 |
1 |
|
|
T1 |
34 |
|
T14 |
18 |
|
T16 |
21437 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12052013 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
664636 |
1 |
|
|
T14 |
2 |
|
T16 |
2671 |
|
T112 |
95 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460828 |
1 |
|
|
T32 |
231 |
|
T1 |
53 |
|
T11 |
483 |
| auto[1] |
5255821 |
1 |
|
|
T1 |
6 |
|
T14 |
14 |
|
T16 |
21216 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2296713 |
1 |
|
|
T14 |
8 |
|
T16 |
9209 |
|
T112 |
217 |
| auto[1] |
auto[0] |
auto[1] |
331827 |
1 |
|
|
T14 |
2 |
|
T16 |
1278 |
|
T112 |
52 |
| auto[1] |
auto[1] |
auto[0] |
2294472 |
1 |
|
|
T1 |
6 |
|
T14 |
4 |
|
T16 |
9336 |
| auto[1] |
auto[1] |
auto[1] |
332809 |
1 |
|
|
T16 |
1393 |
|
T112 |
43 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |