Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425303 |
1 |
|
|
T32 |
231 |
|
T1 |
35 |
|
T11 |
483 |
| auto[1] |
5291346 |
1 |
|
|
T1 |
24 |
|
T14 |
35 |
|
T16 |
21539 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12048366 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
668283 |
1 |
|
|
T14 |
1 |
|
T16 |
2643 |
|
T112 |
107 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443070 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5273579 |
1 |
|
|
T1 |
11 |
|
T14 |
21 |
|
T16 |
21255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2296607 |
1 |
|
|
T1 |
5 |
|
T14 |
4 |
|
T16 |
9666 |
| auto[1] |
auto[0] |
auto[1] |
332733 |
1 |
|
|
T16 |
1413 |
|
T112 |
43 |
|
T2 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2308689 |
1 |
|
|
T1 |
6 |
|
T14 |
16 |
|
T16 |
8946 |
| auto[1] |
auto[1] |
auto[1] |
335550 |
1 |
|
|
T14 |
1 |
|
T16 |
1230 |
|
T112 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |