Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453304 |
1 |
|
|
T32 |
231 |
|
T1 |
36 |
|
T11 |
483 |
| auto[1] |
5263345 |
1 |
|
|
T1 |
23 |
|
T14 |
24 |
|
T16 |
22330 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12052037 |
1 |
|
|
T32 |
231 |
|
T1 |
59 |
|
T11 |
483 |
| auto[1] |
664612 |
1 |
|
|
T16 |
2761 |
|
T112 |
97 |
|
T2 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459159 |
1 |
|
|
T32 |
231 |
|
T1 |
48 |
|
T11 |
483 |
| auto[1] |
5257490 |
1 |
|
|
T1 |
11 |
|
T14 |
10 |
|
T16 |
22176 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2290311 |
1 |
|
|
T1 |
6 |
|
T14 |
6 |
|
T16 |
9508 |
| auto[1] |
auto[0] |
auto[1] |
331671 |
1 |
|
|
T16 |
1352 |
|
T112 |
34 |
|
T2 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2302567 |
1 |
|
|
T1 |
5 |
|
T14 |
4 |
|
T16 |
9907 |
| auto[1] |
auto[1] |
auto[1] |
332941 |
1 |
|
|
T16 |
1409 |
|
T112 |
63 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |